ATE442666T1 - Optimiertes verfahren zur herstellung einer metallsicherung in einer halbleitervorrichtung - Google Patents

Optimiertes verfahren zur herstellung einer metallsicherung in einer halbleitervorrichtung

Info

Publication number
ATE442666T1
ATE442666T1 AT01000649T AT01000649T ATE442666T1 AT E442666 T1 ATE442666 T1 AT E442666T1 AT 01000649 T AT01000649 T AT 01000649T AT 01000649 T AT01000649 T AT 01000649T AT E442666 T1 ATE442666 T1 AT E442666T1
Authority
AT
Austria
Prior art keywords
oxide
producing
semiconductor device
metal fuse
fuse
Prior art date
Application number
AT01000649T
Other languages
English (en)
Inventor
Melissa M Hewson
Ricky A Jackson
Abha Singh
Toan Tran
Howard Tigelaar
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of ATE442666T1 publication Critical patent/ATE442666T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
    • H10W20/494—Fuses, i.e. interconnections changeable from conductive to non-conductive changeable by the use of an external beam, e.g. laser beam or ion beam
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49107—Fuse making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
AT01000649T 2000-11-30 2001-11-21 Optimiertes verfahren zur herstellung einer metallsicherung in einer halbleitervorrichtung ATE442666T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US25032400P 2000-11-30 2000-11-30

Publications (1)

Publication Number Publication Date
ATE442666T1 true ATE442666T1 (de) 2009-09-15

Family

ID=22947265

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01000649T ATE442666T1 (de) 2000-11-30 2001-11-21 Optimiertes verfahren zur herstellung einer metallsicherung in einer halbleitervorrichtung

Country Status (5)

Country Link
US (1) US6687973B2 (de)
EP (1) EP1211723B1 (de)
JP (1) JP4118044B2 (de)
AT (1) ATE442666T1 (de)
DE (1) DE60139850D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004055876A (ja) * 2002-07-22 2004-02-19 Renesas Technology Corp 半導体装置及び半導体装置の製造方法
US6835642B2 (en) * 2002-12-18 2004-12-28 Taiwan Semiconductor Manufacturing Co., Ltd Method of forming a metal fuse on semiconductor devices
JP2004311638A (ja) 2003-04-04 2004-11-04 Renesas Technology Corp 半導体装置
US20050285222A1 (en) 2004-06-29 2005-12-29 Kong-Beng Thei New fuse structure
DE102006046790B4 (de) 2006-10-02 2014-01-02 Infineon Technologies Ag Integriertes Bauelement und Verfahren zum Trennen einer elektrisch leitfähigen Verbindung
US20100117190A1 (en) * 2008-11-13 2010-05-13 Harry Chuang Fuse structure for intergrated circuit devices
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57202778A (en) * 1981-06-08 1982-12-11 Nippon Telegr & Teleph Corp <Ntt> Substrate for semiconductor integrated circuit and manufacture thereof
TW299897U (en) * 1993-11-05 1997-03-01 Semiconductor Energy Lab A semiconductor integrated circuit
US5521116A (en) * 1995-04-24 1996-05-28 Texas Instruments Incorporated Sidewall formation process for a top lead fuse
US5747868A (en) * 1995-06-26 1998-05-05 Alliance Semiconductor Corporation Laser fusible link structure for semiconductor devices
US6100118A (en) * 1998-06-11 2000-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fabrication of metal fuse design for redundancy technology having a guard ring
US6261873B1 (en) * 1999-04-29 2001-07-17 International Business Machines Corporation Pedestal fuse
US6214681B1 (en) * 2000-01-26 2001-04-10 Advanced Micro Devices, Inc. Process for forming polysilicon/germanium thin films without germanium outgassing
JP3851752B2 (ja) * 2000-03-27 2006-11-29 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
US20020062549A1 (en) 2002-05-30
EP1211723B1 (de) 2009-09-09
EP1211723A2 (de) 2002-06-05
DE60139850D1 (de) 2009-10-22
EP1211723A3 (de) 2006-04-05
JP2002203902A (ja) 2002-07-19
JP4118044B2 (ja) 2008-07-16
US6687973B2 (en) 2004-02-10

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Legal Events

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