ATE444526T1 - Cache-speicher-trashings-verringerung von bestimmten code-stücken - Google Patents

Cache-speicher-trashings-verringerung von bestimmten code-stücken

Info

Publication number
ATE444526T1
ATE444526T1 AT04713597T AT04713597T ATE444526T1 AT E444526 T1 ATE444526 T1 AT E444526T1 AT 04713597 T AT04713597 T AT 04713597T AT 04713597 T AT04713597 T AT 04713597T AT E444526 T1 ATE444526 T1 AT E444526T1
Authority
AT
Austria
Prior art keywords
memory portion
instruction cache
instruction
memory
instructions
Prior art date
Application number
AT04713597T
Other languages
English (en)
Inventor
Rogier Wester
Gerrit Slavenburg
De Waerdt Jan-Willem Van
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE444526T1 publication Critical patent/ATE444526T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Power Sources (AREA)
AT04713597T 2003-02-24 2004-02-23 Cache-speicher-trashings-verringerung von bestimmten code-stücken ATE444526T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US44887103P 2003-02-24 2003-02-24
PCT/IB2004/000455 WO2004075066A2 (en) 2003-02-24 2004-02-23 Reducing cache trashing of certain pieces

Publications (1)

Publication Number Publication Date
ATE444526T1 true ATE444526T1 (de) 2009-10-15

Family

ID=32908665

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04713597T ATE444526T1 (de) 2003-02-24 2004-02-23 Cache-speicher-trashings-verringerung von bestimmten code-stücken

Country Status (8)

Country Link
US (1) US7353337B2 (de)
EP (1) EP1599803B1 (de)
JP (1) JP2006518896A (de)
KR (1) KR100985239B1 (de)
CN (1) CN1777875B (de)
AT (1) ATE444526T1 (de)
DE (1) DE602004023372D1 (de)
WO (1) WO2004075066A2 (de)

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US7263587B1 (en) * 2003-06-27 2007-08-28 Zoran Corporation Unified memory controller
KR100735552B1 (ko) 2005-09-23 2007-07-04 삼성전자주식회사 코드 메모리 상의 프로그램의 코드 크기를 줄이는 방법
US7689772B2 (en) * 2006-05-04 2010-03-30 Intel Corporation Power-performance modulation in caches using a smart least recently used scheme
US7747820B2 (en) * 2007-06-15 2010-06-29 Microsoft Corporation Managing working set use of a cache via page coloring
CN101753282B (zh) * 2008-12-22 2013-06-19 电信科学技术研究院 一种进程缓存的配置和处理的方法及系统
FR2962567B1 (fr) * 2010-07-12 2013-04-26 Bull Sas Procede d'optimisation d'acces memoire, lors de la reprise d'execution d'une application, dans un microprocesseur comprenant plusieurs coeurs logiques et programme d'ordinateur mettant en oeuvre un tel procede
US9104532B2 (en) * 2012-12-14 2015-08-11 International Business Machines Corporation Sequential location accesses in an active memory device
WO2014143036A1 (en) 2013-03-15 2014-09-18 Intel Corporation Method for pinning data in large cache in multi-level memory system
US9558124B2 (en) * 2013-11-08 2017-01-31 Seagate Technology Llc Data storage system with passive partitioning in a secondary memory
CN105706049B (zh) * 2014-01-27 2019-04-16 上海兆芯集成电路有限公司 操作系统例行程序的预测历程储存器的部分使用
US10235203B1 (en) 2014-03-31 2019-03-19 EMC IP Holding Company LLC Techniques for increasing storage system performance in processor-bound workloads with large working sets and poor spatial locality

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Publication number Priority date Publication date Assignee Title
US4463424A (en) * 1981-02-19 1984-07-31 International Business Machines Corporation Method for dynamically allocating LRU/MRU managed memory among concurrent sequential processes
EP0389151A3 (de) * 1989-03-22 1992-06-03 International Business Machines Corporation System und Verfahren für die Verwaltung eines verteilten Cache-Speichers
US5394531A (en) * 1989-04-03 1995-02-28 International Business Machines Corporation Dynamic storage allocation system for a prioritized cache
EP0442474B1 (de) * 1990-02-13 1997-07-23 Sanyo Electric Co., Ltd. Vorrichtung und Verfahren zum Steuern eines Cache-Speichers
JPH0799508B2 (ja) * 1990-10-15 1995-10-25 インターナショナル・ビジネス・マシーンズ・コーポレイション キャッシュ記憶機構を動的に区分する方法およびキャッシュ記憶機構システム
US5537635A (en) * 1994-04-04 1996-07-16 International Business Machines Corporation Method and system for assignment of reclaim vectors in a partitioned cache with a virtual minimum partition size
US5696932A (en) * 1995-05-16 1997-12-09 International Business Machines Corporation Method and system for estimating minumun requirements on a cache in a computer based storage system
US5893920A (en) * 1996-09-30 1999-04-13 International Business Machines Corporation System and method for cache management in mobile user file systems
GB9701960D0 (en) * 1997-01-30 1997-03-19 Sgs Thomson Microelectronics A cache system
EP0856798B1 (de) * 1997-01-30 2004-09-29 STMicroelectronics Limited Cachespeichersystem
US6260114B1 (en) * 1997-12-30 2001-07-10 Mcmz Technology Innovations, Llc Computer cache memory windowing
US6370619B1 (en) * 1998-06-22 2002-04-09 Oracle Corporation Managing partitioned cache
US6349363B2 (en) * 1998-12-08 2002-02-19 Intel Corporation Multi-section cache with different attributes for each section
US6898694B2 (en) * 2001-06-28 2005-05-24 Intel Corporation High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle

Also Published As

Publication number Publication date
KR20050115875A (ko) 2005-12-08
EP1599803A2 (de) 2005-11-30
CN1777875B (zh) 2010-04-28
WO2004075066A2 (en) 2004-09-02
WO2004075066A8 (en) 2005-04-07
EP1599803B1 (de) 2009-09-30
KR100985239B1 (ko) 2010-10-04
DE602004023372D1 (de) 2009-11-12
US20060179225A1 (en) 2006-08-10
CN1777875A (zh) 2006-05-24
WO2004075066A3 (en) 2004-10-07
US7353337B2 (en) 2008-04-01
JP2006518896A (ja) 2006-08-17

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