ATE444567T1 - Herstellung von zweifach-gate-logikbauelementen - Google Patents

Herstellung von zweifach-gate-logikbauelementen

Info

Publication number
ATE444567T1
ATE444567T1 AT02735604T AT02735604T ATE444567T1 AT E444567 T1 ATE444567 T1 AT E444567T1 AT 02735604 T AT02735604 T AT 02735604T AT 02735604 T AT02735604 T AT 02735604T AT E444567 T1 ATE444567 T1 AT E444567T1
Authority
AT
Austria
Prior art keywords
gate
self
logic devices
dual gate
aligned
Prior art date
Application number
AT02735604T
Other languages
English (en)
Inventor
Toshiharu Furukawa
Mark Hakey
Steven Holmes
David Horak
William Ma
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE444567T1 publication Critical patent/ATE444567T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/023—Manufacture or treatment of FETs having insulated gates [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01314—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of Ge, C or of compounds of Si, Ge or C contacting the insulator

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
AT02735604T 2001-06-12 2002-05-30 Herstellung von zweifach-gate-logikbauelementen ATE444567T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/879,590 US6596597B2 (en) 2001-06-12 2001-06-12 Method of manufacturing dual gate logic devices
PCT/GB2002/002622 WO2002101834A2 (en) 2001-06-12 2002-05-30 An intermediate manufacture for a dual gate logic device

Publications (1)

Publication Number Publication Date
ATE444567T1 true ATE444567T1 (de) 2009-10-15

Family

ID=25374451

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02735604T ATE444567T1 (de) 2001-06-12 2002-05-30 Herstellung von zweifach-gate-logikbauelementen

Country Status (9)

Country Link
US (2) US6596597B2 (de)
EP (1) EP1396029B1 (de)
JP (1) JP4256772B2 (de)
KR (1) KR100586770B1 (de)
CN (1) CN1291499C (de)
AT (1) ATE444567T1 (de)
DE (1) DE60233872D1 (de)
TW (1) TW564468B (de)
WO (1) WO2002101834A2 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6798017B2 (en) * 2001-08-31 2004-09-28 International Business Machines Corporation Vertical dual gate field effect transistor
US6580132B1 (en) * 2002-04-10 2003-06-17 International Business Machines Corporation Damascene double-gate FET
US7019342B2 (en) 2003-07-03 2006-03-28 American Semiconductor, Inc. Double-gated transistor circuit
US7015547B2 (en) 2003-07-03 2006-03-21 American Semiconductor, Inc. Multi-configurable independently multi-gated MOSFET
US6919647B2 (en) * 2003-07-03 2005-07-19 American Semiconductor, Inc. SRAM cell
US7078300B2 (en) * 2003-09-27 2006-07-18 International Business Machines Corporation Thin germanium oxynitride gate dielectric for germanium-based devices
US7098477B2 (en) * 2004-04-23 2006-08-29 International Business Machines Corporation Structure and method of manufacturing a finFET device having stacked fins
US7348641B2 (en) * 2004-08-31 2008-03-25 International Business Machines Corporation Structure and method of making double-gated self-aligned finFET having gates of different lengths
US7176090B2 (en) * 2004-09-07 2007-02-13 Intel Corporation Method for making a semiconductor device that includes a metal gate electrode
FR2893762B1 (fr) * 2005-11-18 2007-12-21 Commissariat Energie Atomique Procede de realisation de transistor a double grilles auto-alignees par reduction de motifs de grille
US7704838B2 (en) * 2006-08-25 2010-04-27 Freescale Semiconductor, Inc. Method for forming an independent bottom gate connection for buried interconnection including bottom gate of a planar double gate MOSFET
US8530972B2 (en) * 2006-08-25 2013-09-10 Freescale Semiconductor, Inc. Double gate MOSFET with coplanar surfaces for contacting source, drain, and bottom gate
FR2911004B1 (fr) * 2006-12-28 2009-05-15 Commissariat Energie Atomique Procede de realisation de transistors a double-grille asymetriques permettant la realisation de transistors a double-grille asymetriques et symetriques sur un meme substrat
US20090003083A1 (en) * 2007-06-28 2009-01-01 Sandisk 3D Llc Memory cell with voltage modulated sidewall poly resistor
US8478692B2 (en) 2008-06-26 2013-07-02 Visa International Service Association Systems and methods for geographic location notifications of payment transactions
US9542687B2 (en) 2008-06-26 2017-01-10 Visa International Service Association Systems and methods for visual representation of offers
MX2011003199A (es) 2008-09-25 2011-05-25 Visa Int Service Ass Sistemas y metodos para clasificar mensajes de alerta y de oferta en un dispositivo movil.
US8159327B2 (en) 2008-11-13 2012-04-17 Visa International Service Association Device including authentication glyph
US9312230B2 (en) * 2010-02-08 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar structure for semiconductor substrate and method of manufacture
JP5364668B2 (ja) * 2010-09-22 2013-12-11 株式会社東芝 赤外線撮像装置
JP5933300B2 (ja) * 2011-03-16 2016-06-08 株式会社半導体エネルギー研究所 半導体装置
US8739078B2 (en) 2012-01-18 2014-05-27 International Business Machines Corporation Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications
FR2987709B1 (fr) * 2012-03-05 2017-04-28 Soitec Silicon On Insulator Table de correspondance
US9178077B2 (en) 2012-11-13 2015-11-03 Micron Technology, Inc. Semiconductor constructions
US9105737B2 (en) 2013-01-07 2015-08-11 Micron Technology, Inc. Semiconductor constructions
US8853769B2 (en) 2013-01-10 2014-10-07 Micron Technology, Inc. Transistors and semiconductor constructions
US9219070B2 (en) 2013-02-05 2015-12-22 Micron Technology, Inc. 3-D memory arrays
US9159845B2 (en) 2013-05-15 2015-10-13 Micron Technology, Inc. Charge-retaining transistor, array of memory cells, and methods of forming a charge-retaining transistor
KR102102783B1 (ko) 2014-01-06 2020-04-22 삼성전자주식회사 반도체 소자, 자기 기억 소자 및 이들의 제조 방법
KR102191217B1 (ko) * 2014-04-28 2020-12-16 삼성전자주식회사 반도체 소자, 자기 기억 소자 및 이들의 제조 방법
US10103262B2 (en) * 2016-01-12 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a finFET structure with high quality EPI film
US10176870B1 (en) 2017-07-05 2019-01-08 Micron Technology, Inc. Multifunctional memory cells
US10262736B2 (en) 2017-07-05 2019-04-16 Micron Technology, Inc. Multifunctional memory cells
US10727216B1 (en) 2019-05-10 2020-07-28 Sandisk Technologies Llc Method for removing a bulk substrate from a bonded assembly of wafers
US11482423B2 (en) * 2021-01-28 2022-10-25 Tokyo Electron Limited Plasma etching techniques
US12191205B2 (en) * 2021-07-09 2025-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5324673A (en) * 1992-11-19 1994-06-28 Motorola, Inc. Method of formation of vertical transistor
US5612552A (en) * 1994-03-31 1997-03-18 Lsi Logic Corporation Multilevel gate array integrated circuit structure with perpendicular access to all active device regions
US5583368A (en) * 1994-08-11 1996-12-10 International Business Machines Corporation Stacked devices
KR100212693B1 (ko) * 1996-12-14 1999-08-02 권혁준 규소/규소게르마늄 모스 전계 트랜지스터 및 그 제조방법
FR2791177A1 (fr) * 1999-03-19 2000-09-22 France Telecom Procede de realisation d'une grille en forme de champignon ou grille en "t"
US6509586B2 (en) * 2000-03-31 2003-01-21 Fujitsu Limited Semiconductor device, method for fabricating the semiconductor device and semiconductor integrated circuit
JP2001332630A (ja) * 2000-05-19 2001-11-30 Sharp Corp 半導体装置の製造方法
US6429484B1 (en) * 2000-08-07 2002-08-06 Advanced Micro Devices, Inc. Multiple active layer structure and a method of making such a structure
KR100354438B1 (ko) * 2000-12-12 2002-09-28 삼성전자 주식회사 모스 트랜지스터의 실리콘 게르마늄 게이트 폴리 형성방법 및 이를 이용한 씨모스 트랜지스터 형성 방법
US6518106B2 (en) * 2001-05-26 2003-02-11 Motorola, Inc. Semiconductor device and a method therefor

Also Published As

Publication number Publication date
CN1516902A (zh) 2004-07-28
WO2002101834A3 (en) 2003-05-30
US6891226B2 (en) 2005-05-10
US6596597B2 (en) 2003-07-22
JP2004529509A (ja) 2004-09-24
WO2002101834A2 (en) 2002-12-19
EP1396029B1 (de) 2009-09-30
EP1396029A2 (de) 2004-03-10
DE60233872D1 (de) 2009-11-12
KR100586770B1 (ko) 2006-06-08
US20030201500A1 (en) 2003-10-30
CN1291499C (zh) 2006-12-20
US20020187610A1 (en) 2002-12-12
JP4256772B2 (ja) 2009-04-22
TW564468B (en) 2003-12-01
KR20040006032A (ko) 2004-01-16

Similar Documents

Publication Publication Date Title
ATE444567T1 (de) Herstellung von zweifach-gate-logikbauelementen
US6818490B2 (en) Method of fabricating complementary high-voltage field-effect transistors
EP3217432B1 (de) Zum hochspannungsbetrieb fähiges halbleiterbauelement
US20070190740A1 (en) Enhanced silicon-on-insulator (soi) transistors and methods of making enhanced soi transistors
TW328615B (en) MOSFET device and method of controlling dopant diffusion and metal contamination in thin polycide gate conductor
WO2002029900A3 (en) Silicon carbide power mosfets having a shorting channel and methods of fabrication them
TWI268557B (en) Semiconductor device, accumulation mode multiple-gate transistor and methods of fabricating the same
US20090014784A1 (en) Vertical mos transistor and method therefor
US20130154011A1 (en) Methods and Apparatus for Reduced Gate Resistance FinFET
TW541696B (en) Semiconductor component and method of manufacturing
EP3217431A1 (de) Zum hochspannungsbetrieb fähiges halbleiterbauelement
US10586854B2 (en) Gate-all-around field effect transistor having multiple threshold voltages
WO2003098700A3 (en) Resurf super-junction devices having trenches
CN101410951B (zh) 低栅极感生的漏极泄漏的金属氧化物半导体场效应晶体管结构及其制备方法
US12230693B2 (en) Semiconductor device and manufacturing method therefor
TW357386B (en) Insulating gate-type semiconductor and the manufacturing method
TWI246120B (en) A high voltage semiconductor device utilizing a deep trench structure
KR101297440B1 (ko) Ｐｎ접합 및 모스 커패시터 하이브리드 리설프 트랜지스터
WO2005034186A3 (en) Method for forming a semiconductor device having isolation regions
EP0239250A3 (de) MOS-Transistor mit kurzer Kanallänge
CN110896104A (zh) 多重栅极功率mosfet元件
US20070132016A1 (en) Trench ld structure
EP3035388A1 (de) Halbleitervorrichtung und Herstellungsverfahren dafür
KR20110078946A (ko) 반도체 소자 및 그의 제조방법
WO2003009374A1 (en) Production method of semiconductor device

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties