ATE453152T1 - Multiprozessorsystem mit gemeinsamem speicher, welches gemischte broadcast-snoop und verzeichnisbasierte kohärenzprotokolle benutzt - Google Patents

Multiprozessorsystem mit gemeinsamem speicher, welches gemischte broadcast-snoop und verzeichnisbasierte kohärenzprotokolle benutzt

Info

Publication number
ATE453152T1
ATE453152T1 AT01303988T AT01303988T ATE453152T1 AT E453152 T1 ATE453152 T1 AT E453152T1 AT 01303988 T AT01303988 T AT 01303988T AT 01303988 T AT01303988 T AT 01303988T AT E453152 T1 ATE453152 T1 AT E453152T1
Authority
AT
Austria
Prior art keywords
mode
point
network
address
broadcast
Prior art date
Application number
AT01303988T
Other languages
English (en)
Inventor
Robert Cypher
Ashok Singhal
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE453152T1 publication Critical patent/ATE453152T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT01303988T 2001-05-01 2001-05-01 Multiprozessorsystem mit gemeinsamem speicher, welches gemischte broadcast-snoop und verzeichnisbasierte kohärenzprotokolle benutzt ATE453152T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01303988A EP1255201B1 (de) 2001-05-01 2001-05-01 Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutzt

Publications (1)

Publication Number Publication Date
ATE453152T1 true ATE453152T1 (de) 2010-01-15

Family

ID=8181936

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01303988T ATE453152T1 (de) 2001-05-01 2001-05-01 Multiprozessorsystem mit gemeinsamem speicher, welches gemischte broadcast-snoop und verzeichnisbasierte kohärenzprotokolle benutzt

Country Status (4)

Country Link
US (1) US7032078B2 (de)
EP (1) EP1255201B1 (de)
AT (1) ATE453152T1 (de)
DE (1) DE60140859D1 (de)

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US8468308B2 (en) * 2004-01-20 2013-06-18 Hewlett-Packard Development Company, L.P. System and method for non-migratory requests in a cache coherency protocol
US7177987B2 (en) * 2004-01-20 2007-02-13 Hewlett-Packard Development Company, L.P. System and method for responses between different cache coherency protocols
US7620696B2 (en) * 2004-01-20 2009-11-17 Hewlett-Packard Development Company, L.P. System and method for conflict responses in a cache coherency protocol
US7143245B2 (en) * 2004-01-20 2006-11-28 Hewlett-Packard Development Company, L.P. System and method for read migratory optimization in a cache coherency protocol
US7818391B2 (en) * 2004-01-20 2010-10-19 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration
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US8145847B2 (en) * 2004-01-20 2012-03-27 Hewlett-Packard Development Company, L.P. Cache coherency protocol with ordering points
US7149852B2 (en) * 2004-01-20 2006-12-12 Hewlett Packard Development Company, Lp. System and method for blocking data responses
US7769959B2 (en) * 2004-01-20 2010-08-03 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration to memory
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US7480770B2 (en) * 2006-06-14 2009-01-20 Sun Microsystems, Inc. Semi-blocking deterministic directory coherence
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US20160184571A1 (en) * 2013-09-09 2016-06-30 Nanopass Technologies Ltd. Prefilled Syringe Devices Employing Microneedle Interfaces for Intradermal Delivery
US9298623B2 (en) 2013-09-26 2016-03-29 Globalfoundries Inc. Identifying high-conflict cache lines in transactional memory computing environments
US9298626B2 (en) 2013-09-26 2016-03-29 Globalfoundries Inc. Managing high-conflict cache lines in transactional memory computing environments
US9329890B2 (en) 2013-09-26 2016-05-03 Globalfoundries Inc. Managing high-coherence-miss cache lines in multi-processor computing environments
US9292444B2 (en) 2013-09-26 2016-03-22 International Business Machines Corporation Multi-granular cache management in multi-processor computing environments
US9086974B2 (en) * 2013-09-26 2015-07-21 International Business Machines Corporation Centralized management of high-contention cache lines in multi-processor computing environments
KR102069696B1 (ko) * 2013-11-20 2020-01-23 한국전자통신연구원 캐시 제어 장치 및 방법
US10255183B2 (en) 2015-07-23 2019-04-09 Arteris, Inc. Victim buffer for cache coherent systems
US12026095B2 (en) 2014-12-30 2024-07-02 Arteris, Inc. Cache coherent system implementing victim buffers
US9542316B1 (en) * 2015-07-23 2017-01-10 Arteris, Inc. System and method for adaptation of coherence models between agents
US11656992B2 (en) * 2019-05-03 2023-05-23 Western Digital Technologies, Inc. Distributed cache with in-network prefetch
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US11675706B2 (en) 2020-06-30 2023-06-13 Western Digital Technologies, Inc. Devices and methods for failure detection and recovery for a distributed cache
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Also Published As

Publication number Publication date
DE60140859D1 (de) 2010-02-04
EP1255201A1 (de) 2002-11-06
US20030018739A1 (en) 2003-01-23
EP1255201B1 (de) 2009-12-23
US7032078B2 (en) 2006-04-18

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