ATE453985T1 - System und verfahren zur behandlung in einem verbindungsnetzwerk transportierter nachrichten - Google Patents
System und verfahren zur behandlung in einem verbindungsnetzwerk transportierter nachrichtenInfo
- Publication number
- ATE453985T1 ATE453985T1 AT07108875T AT07108875T ATE453985T1 AT E453985 T1 ATE453985 T1 AT E453985T1 AT 07108875 T AT07108875 T AT 07108875T AT 07108875 T AT07108875 T AT 07108875T AT E453985 T1 ATE453985 T1 AT E453985T1
- Authority
- AT
- Austria
- Prior art keywords
- message
- priority
- request message
- destination
- connecting network
- Prior art date
Links
- 239000003795 chemical substances by application Substances 0.000 abstract 3
- 239000003999 initiator Substances 0.000 abstract 1
- 230000001902 propagating effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
- H04L47/2408—Traffic characterised by specific attributes, e.g. priority or QoS for supporting different services, e.g. a differentiated services [DiffServ] type of service
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/15—Flow control; Congestion control in relation to multipoint traffic
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/70—Admission control; Resource allocation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/70—Admission control; Resource allocation
- H04L47/78—Architectures of resource allocation
- H04L47/781—Centralised allocation of resources
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/70—Admission control; Resource allocation
- H04L47/80—Actions related to the user profile or the type of traffic
- H04L47/805—QOS or priority aware
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer And Data Communications (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Multi Processors (AREA)
- Selective Calling Equipment (AREA)
- Studio Devices (AREA)
- Information Transfer Between Computers (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0605646A FR2902957B1 (fr) | 2006-06-23 | 2006-06-23 | Systeme et procede de gestions de messages transmis dans un reseau d'interconnexions |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE453985T1 true ATE453985T1 (de) | 2010-01-15 |
Family
ID=37757186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT07108875T ATE453985T1 (de) | 2006-06-23 | 2007-05-24 | System und verfahren zur behandlung in einem verbindungsnetzwerk transportierter nachrichten |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8254380B2 (de) |
| EP (1) | EP1871058B1 (de) |
| AT (1) | ATE453985T1 (de) |
| DE (1) | DE602007004028D1 (de) |
| FR (1) | FR2902957B1 (de) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9589254B2 (en) * | 2010-12-08 | 2017-03-07 | Microsoft Technology Licensing, Llc | Using e-mail message characteristics for prioritization |
| US11088906B2 (en) * | 2018-05-10 | 2021-08-10 | International Business Machines Corporation | Dependency determination in network environment |
| US11196843B2 (en) * | 2018-09-04 | 2021-12-07 | International Business Machines Corporation | Application data access priority for remote storage systems |
Family Cites Families (60)
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| US2243851A (en) * | 1940-06-06 | 1941-06-03 | Bell Telephone Labor Inc | Wire line transmission |
| US5764093A (en) * | 1981-11-28 | 1998-06-09 | Advantest Corporation | Variable delay circuit |
| JPH0388019A (ja) * | 1989-08-31 | 1991-04-12 | Toshiba Corp | データ処理装置 |
| US5313649A (en) * | 1991-05-28 | 1994-05-17 | International Business Machines Corporation | Switch queue structure for one-network parallel processor systems |
| KR970005124B1 (ko) * | 1991-08-14 | 1997-04-12 | 가부시끼가이샤 아드반테스트 | 가변지연회로 |
| US5473761A (en) * | 1991-12-17 | 1995-12-05 | Dell Usa, L.P. | Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by interspersing no operation requests between transfer requests |
| JPH0613857A (ja) * | 1992-06-25 | 1994-01-21 | Fujitsu Ltd | ディレイ調整回路 |
| US5544203A (en) * | 1993-02-17 | 1996-08-06 | Texas Instruments Incorporated | Fine resolution digital delay line with coarse and fine adjustment stages |
| US5541932A (en) * | 1994-06-13 | 1996-07-30 | Xerox Corporation | Circuit for freezing the data in an interface buffer |
| US5453982A (en) * | 1994-08-29 | 1995-09-26 | Hewlett-Packard Company | Packet control procedure between a host processor and a peripheral unit |
| JP2771464B2 (ja) * | 1994-09-29 | 1998-07-02 | 日本電気アイシーマイコンシステム株式会社 | ディジタルpll回路 |
| DE69615471T2 (de) * | 1995-07-07 | 2002-05-08 | Sun Microsystems, Inc. | Verfahren und Vorrichtung zur dynamischen Berechnung von Füllungsgraden eines synchronen Fifo-Puffer |
| EP0752642B1 (de) | 1995-07-07 | 2001-09-26 | Sun Microsystems, Inc. | Verfahren und Vorrichtung zur dynamischen Berechnung von Füllungsgraden eines synchronen Fifo-Puffer |
| US5651002A (en) * | 1995-07-12 | 1997-07-22 | 3Com Corporation | Internetworking device with enhanced packet header translation and memory |
| US5784374A (en) * | 1996-02-06 | 1998-07-21 | Advanced Micro Devices, Inc. | Contention resolution system in ATM switch |
| GB9617553D0 (en) * | 1996-08-21 | 1996-10-02 | Walker Christopher P H | Communication system with improved routing switch |
| US6151316A (en) * | 1997-02-14 | 2000-11-21 | Advanced Micro Devices, Inc. | Apparatus and method for synthesizing management packets for transmission between a network switch and a host controller |
| US6211739B1 (en) * | 1997-06-03 | 2001-04-03 | Cypress Semiconductor Corp. | Microprocessor controlled frequency lock loop for use with an external periodic signal |
| JP3560780B2 (ja) * | 1997-07-29 | 2004-09-02 | 富士通株式会社 | 可変遅延回路及び半導体集積回路装置 |
| US6269433B1 (en) * | 1998-04-29 | 2001-07-31 | Compaq Computer Corporation | Memory controller using queue look-ahead to reduce memory latency |
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| US6778545B1 (en) * | 1998-09-24 | 2004-08-17 | Cisco Technology, Inc. | DSP voice buffersize negotiation between DSPs for voice packet end devices |
| EP1549005B1 (de) * | 1998-12-03 | 2009-03-11 | Secretary of Agency of Industrial Science and Technology | Kommunikationsverfahren und -system |
| US6721309B1 (en) * | 1999-05-18 | 2004-04-13 | Alcatel | Method and apparatus for maintaining packet order integrity in parallel switching engine |
| US6400720B1 (en) * | 1999-06-21 | 2002-06-04 | General Instrument Corporation | Method for transporting variable length and fixed length packets in a standard digital transmission frame |
| JP2001084763A (ja) * | 1999-09-08 | 2001-03-30 | Mitsubishi Electric Corp | クロック発生回路およびそれを具備した半導体記憶装置 |
| US6661303B1 (en) * | 1999-11-30 | 2003-12-09 | International Business Machines Corporation | Cross talk suppression in a bidirectional bus |
| US6651148B2 (en) * | 2000-05-23 | 2003-11-18 | Canon Kabushiki Kaisha | High-speed memory controller for pipelining memory read transactions |
| ATE370448T1 (de) | 2000-06-09 | 2007-09-15 | Univ Columbia | Fifo schaltungen mit niedriger verzögerung für gemischte synchrone und asynchrone systeme |
| US7266613B1 (en) * | 2000-08-09 | 2007-09-04 | Microsoft Corporation | Fast dynamic measurement of bandwidth in a TCP network environment |
| EP1182819B1 (de) * | 2000-08-23 | 2006-10-04 | Sony Deutschland GmbH | Fernbedienung eines Hausnetzwerks mittels elektronischer Post |
| FR2814007B1 (fr) | 2000-09-08 | 2003-01-31 | France Telecom | Oscillateur commande en tension |
| US6850542B2 (en) * | 2000-11-14 | 2005-02-01 | Broadcom Corporation | Linked network switch configuration |
| US6976201B2 (en) * | 2000-11-22 | 2005-12-13 | Silicon Image | Method and system for host handling of communications errors |
| KR100467643B1 (ko) * | 2000-12-28 | 2005-01-24 | 엘지전자 주식회사 | 무선 랜에서의 멀티미디어 데이터 전송 방법 |
| US20040128413A1 (en) * | 2001-06-08 | 2004-07-01 | Tiberiu Chelcea | Low latency fifo circuits for mixed asynchronous and synchronous systems |
| US7164678B2 (en) * | 2001-06-25 | 2007-01-16 | Intel Corporation | Control of processing order for received network packets |
| US6886048B2 (en) | 2001-11-15 | 2005-04-26 | Hewlett-Packard Development Company, L.P. | Techniques for processing out-of-order requests in a processor-based system |
| US6759911B2 (en) * | 2001-11-19 | 2004-07-06 | Mcron Technology, Inc. | Delay-locked loop circuit and method using a ring oscillator and counter-based delay |
| US7292594B2 (en) * | 2002-06-10 | 2007-11-06 | Lsi Corporation | Weighted fair share scheduler for large input-buffered high-speed cross-point packet/cell switches |
| US7200137B2 (en) * | 2002-07-29 | 2007-04-03 | Freescale Semiconductor, Inc. | On chip network that maximizes interconnect utilization between processing elements |
| US7051150B2 (en) * | 2002-07-29 | 2006-05-23 | Freescale Semiconductor, Inc. | Scalable on chip network |
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| JP4134916B2 (ja) * | 2003-02-14 | 2008-08-20 | 松下電器産業株式会社 | ネットワーク接続装置、およびネットワーク接続切替方法 |
| US6812760B1 (en) * | 2003-07-02 | 2004-11-02 | Micron Technology, Inc. | System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits |
| FR2857114B1 (fr) * | 2003-07-04 | 2005-09-30 | Arteris | Systeme et procede de communication entre des modules |
| FR2858148B1 (fr) * | 2003-07-22 | 2005-09-30 | Arteris | Dispositif et procede de transmission d'un message |
| FR2858895B1 (fr) * | 2003-08-13 | 2006-05-05 | Arteris | Procede et dispositif de gestion de priorite lors de la transmission d'un message |
| FR2860663B1 (fr) * | 2003-10-01 | 2006-09-01 | Arteris | Dispositif de retard numerique, oscillateur numerique generateur de signal d'horloge, et interface memoire |
| FR2862457B1 (fr) * | 2003-11-13 | 2006-02-24 | Arteris | Systeme et procede de transmission d'une sequence de messages dans un reseau d'interconnexions. |
| FR2863377B1 (fr) * | 2003-12-09 | 2006-02-17 | Arteris | Procede de gestion d'un dispositif de memorisation de donnees organisees en file d'attente, et dispositif associe |
| US7324541B2 (en) * | 2003-12-22 | 2008-01-29 | Intel Corporation | Switching device utilizing internal priority assignments |
| FR2865334B1 (fr) * | 2004-01-21 | 2006-03-03 | Arteris | Procede et systeme de transmission de messages dans un reseau d'interconnexions. |
| FR2867338B1 (fr) * | 2004-03-02 | 2007-08-10 | Arteris | Procede et dispositif de commutation entre des agents |
| US20080205432A1 (en) * | 2005-04-07 | 2008-08-28 | Koninklijke Philips Electronics, N.V. | Network-On-Chip Environment and Method For Reduction of Latency |
| FR2887093B1 (fr) * | 2005-06-10 | 2007-08-31 | Arteris Sa | Systeme et procede de transmission de donnees dans un circuit electronique |
| FR2890766B1 (fr) * | 2005-09-12 | 2007-11-30 | Arteris Sa | Systeme et procede de communication asynchrone sur circuit, entre des sous-circuits synchrones |
| FR2893471B1 (fr) * | 2005-11-16 | 2008-01-25 | Arteris Sa | Systeme et procede de routage statique de flux de paquets de donnees dans un reseau d'interconnexion |
-
2006
- 2006-06-23 FR FR0605646A patent/FR2902957B1/fr not_active Expired - Fee Related
- 2006-09-06 US US11/516,811 patent/US8254380B2/en not_active Expired - Fee Related
-
2007
- 2007-05-24 DE DE602007004028T patent/DE602007004028D1/de not_active Expired - Fee Related
- 2007-05-24 AT AT07108875T patent/ATE453985T1/de not_active IP Right Cessation
- 2007-05-24 EP EP07108875A patent/EP1871058B1/de not_active Not-in-force
Also Published As
| Publication number | Publication date |
|---|---|
| FR2902957B1 (fr) | 2008-09-12 |
| EP1871058B1 (de) | 2009-12-30 |
| EP1871058A1 (de) | 2007-12-26 |
| FR2902957A1 (fr) | 2007-12-28 |
| US8254380B2 (en) | 2012-08-28 |
| US20070297404A1 (en) | 2007-12-27 |
| DE602007004028D1 (de) | 2010-02-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |