ATE455330T1 - Dsp-architektur für drahtlose im basisband arbeitende anwendungen - Google Patents

Dsp-architektur für drahtlose im basisband arbeitende anwendungen

Info

Publication number
ATE455330T1
ATE455330T1 AT02773433T AT02773433T ATE455330T1 AT E455330 T1 ATE455330 T1 AT E455330T1 AT 02773433 T AT02773433 T AT 02773433T AT 02773433 T AT02773433 T AT 02773433T AT E455330 T1 ATE455330 T1 AT E455330T1
Authority
AT
Austria
Prior art keywords
processing elements
reconfigurable
array
channel
frame buffer
Prior art date
Application number
AT02773433T
Other languages
English (en)
Inventor
Behzad Mohebbi
Fadi Kurdahi
Original Assignee
Finlasin Technology Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Finlasin Technology Llc filed Critical Finlasin Technology Llc
Application granted granted Critical
Publication of ATE455330T1 publication Critical patent/ATE455330T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Transceivers (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Microcomputers (AREA)
  • Executing Machine-Instructions (AREA)
AT02773433T 2001-09-17 2002-09-17 Dsp-architektur für drahtlose im basisband arbeitende anwendungen ATE455330T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US32376301P 2001-09-17 2001-09-17
PCT/US2002/029490 WO2003025782A2 (en) 2001-09-17 2002-09-17 Digital signal processor for wireless baseband processing

Publications (1)

Publication Number Publication Date
ATE455330T1 true ATE455330T1 (de) 2010-01-15

Family

ID=23260608

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02773433T ATE455330T1 (de) 2001-09-17 2002-09-17 Dsp-architektur für drahtlose im basisband arbeitende anwendungen

Country Status (6)

Country Link
US (1) US7007155B2 (de)
EP (1) EP1436721B1 (de)
AT (1) ATE455330T1 (de)
AU (1) AU2002336576A1 (de)
DE (1) DE60235102D1 (de)
WO (1) WO2003025782A2 (de)

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Also Published As

Publication number Publication date
WO2003025782A3 (en) 2004-04-29
EP1436721B1 (de) 2010-01-13
EP1436721A2 (de) 2004-07-14
US7007155B2 (en) 2006-02-28
AU2002336576A1 (en) 2003-04-01
WO2003025782A2 (en) 2003-03-27
US20030108119A1 (en) 2003-06-12
DE60235102D1 (de) 2010-03-04

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