ATE456882T1 - Konfiguriebare seriellschnittstelle für programmierbare logikschaltung - Google Patents

Konfiguriebare seriellschnittstelle für programmierbare logikschaltung

Info

Publication number
ATE456882T1
ATE456882T1 AT06005634T AT06005634T ATE456882T1 AT E456882 T1 ATE456882 T1 AT E456882T1 AT 06005634 T AT06005634 T AT 06005634T AT 06005634 T AT06005634 T AT 06005634T AT E456882 T1 ATE456882 T1 AT E456882T1
Authority
AT
Austria
Prior art keywords
stage
circuitry
byte
programmable logic
serial interface
Prior art date
Application number
AT06005634T
Other languages
English (en)
Inventor
Ramanand Venkata
Chong H Lee
Rakesh H Patel
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Application granted granted Critical
Publication of ATE456882T1 publication Critical patent/ATE456882T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Information Transfer Systems (AREA)
AT06005634T 2005-04-18 2006-03-20 Konfiguriebare seriellschnittstelle für programmierbare logikschaltung ATE456882T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67243305P 2005-04-18 2005-04-18
US11/177,034 US7538578B2 (en) 2005-04-18 2005-07-08 Multiple data rates in programmable logic device serial interface

Publications (1)

Publication Number Publication Date
ATE456882T1 true ATE456882T1 (de) 2010-02-15

Family

ID=36645715

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06005634T ATE456882T1 (de) 2005-04-18 2006-03-20 Konfiguriebare seriellschnittstelle für programmierbare logikschaltung

Country Status (6)

Country Link
US (1) US7538578B2 (de)
EP (1) EP1715585B1 (de)
JP (1) JP2006302277A (de)
CN (1) CN1870435B (de)
AT (1) ATE456882T1 (de)
DE (1) DE602006011974D1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4336860B2 (ja) 2007-02-21 2009-09-30 日本電気株式会社 シリアルインタフェース回路、及びシリアル受信器
US8126079B1 (en) * 2007-07-03 2012-02-28 Altera Corporation High-speed serial data signal interface circuitry with multi-data-rate switching capability
US9559881B2 (en) * 2007-12-21 2017-01-31 Altera Corporation Transceiver system with reduced latency uncertainty
JP2010033125A (ja) * 2008-07-25 2010-02-12 Hitachi Ltd ストレージ装置及びデータ転送方法
US8165191B2 (en) * 2008-10-17 2012-04-24 Altera Corporation Multi-protocol channel-aggregated configurable transceiver in an integrated circuit
JP5272926B2 (ja) 2009-06-29 2013-08-28 富士通株式会社 データ送信回路
US9531646B1 (en) 2009-12-07 2016-12-27 Altera Corporation Multi-protocol configurable transceiver including configurable deskew in an integrated circuit
US8477831B2 (en) 2010-02-17 2013-07-02 Altera Corporation Multi-protocol multiple-data-rate auto-speed negotiation architecture for a device
US8406258B1 (en) 2010-04-01 2013-03-26 Altera Corporation Apparatus and methods for low-jitter transceiver clocking
US8732375B1 (en) * 2010-04-01 2014-05-20 Altera Corporation Multi-protocol configurable transceiver with independent channel-based PCS in an integrated circuit
JP5719926B2 (ja) * 2010-06-04 2015-05-20 ザイリンクス インコーポレイテッドＸｉｌｉｎｘ Ｉｎｃｏｒｐｏｒａｔｅｄ 集積回路のための入出力バンクアーキテクチャ
US8488623B2 (en) * 2010-07-28 2013-07-16 Altera Corporation Scalable interconnect modules with flexible channel bonding
US8464088B1 (en) * 2010-10-29 2013-06-11 Altera Corporation Multiple channel bonding in a high speed clock network
CN102340374A (zh) * 2011-07-14 2012-02-01 大唐移动通信设备有限公司 一种速率匹配的方法及装置
US9244872B2 (en) * 2012-12-21 2016-01-26 Ati Technologies Ulc Configurable communications controller
US9106229B1 (en) * 2013-03-14 2015-08-11 Altera Corporation Programmable interposer circuitry
CN105117360B (zh) * 2015-07-29 2019-01-04 国核自仪系统工程有限公司 基于fpga的接口信号重映射方法
US10038450B1 (en) * 2015-12-10 2018-07-31 Xilinx, Inc. Circuits for and methods of transmitting data in an integrated circuit
CN108667824A (zh) * 2018-04-24 2018-10-16 天津芯海创科技有限公司 Pcs协议复用芯片和方法
CN108540489A (zh) * 2018-04-24 2018-09-14 天津芯海创科技有限公司 Pcs协议复用芯片和方法
CN108574695A (zh) * 2018-04-24 2018-09-25 天津芯海创科技有限公司 协议复用芯片和协议复用方法
CN108667825A (zh) * 2018-04-24 2018-10-16 天津芯海创科技有限公司 Pcs协议复用芯片和方法
CN108521430A (zh) * 2018-04-24 2018-09-11 天津芯海创科技有限公司 双协议复用芯片和双协议复用方法
CN110875798B (zh) * 2018-09-03 2022-08-02 中国科学院上海高等研究院 一种可扩展式物理编码子层
CN109962754B (zh) * 2019-02-15 2022-01-18 深圳市紫光同创电子有限公司 适配64b/66b编码的pcs发送装置、接收装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650140B2 (en) 2001-03-19 2003-11-18 Altera Corporation Programmable logic device with high speed serial interface circuitry
US6750675B2 (en) 2001-09-17 2004-06-15 Altera Corporation Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
CN1190925C (zh) * 2001-11-08 2005-02-23 旺玖科技股份有限公司 通用串行总线复合装置及其实现方法
US6724328B1 (en) 2003-06-03 2004-04-20 Altera Corporation Byte alignment for serial data receiver
US6888376B1 (en) 2003-09-24 2005-05-03 Altera Corporation Multiple data rates in programmable logic device serial interface
US7162553B1 (en) * 2004-10-01 2007-01-09 Altera Corporation Correlating high-speed serial interface data and FIFO status signals in programmable logic devices
US7183797B2 (en) * 2004-10-29 2007-02-27 Altera Corporation Next generation 8B10B architecture
US7461192B2 (en) * 2004-12-15 2008-12-02 Rambus Inc. Interface for bridging out-of-band information and preventing false presence detection of terminating devices

Also Published As

Publication number Publication date
JP2006302277A (ja) 2006-11-02
DE602006011974D1 (de) 2010-03-18
EP1715585B1 (de) 2010-01-27
CN1870435B (zh) 2010-11-17
CN1870435A (zh) 2006-11-29
US7538578B2 (en) 2009-05-26
US20060233172A1 (en) 2006-10-19
EP1715585A1 (de) 2006-10-25

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