ATE458332T1 - Schaltungsanordnung und verfahren zum betrieb einer solchen schaltungsanordnung - Google Patents

Schaltungsanordnung und verfahren zum betrieb einer solchen schaltungsanordnung

Info

Publication number
ATE458332T1
ATE458332T1 AT05735281T AT05735281T ATE458332T1 AT E458332 T1 ATE458332 T1 AT E458332T1 AT 05735281 T AT05735281 T AT 05735281T AT 05735281 T AT05735281 T AT 05735281T AT E458332 T1 ATE458332 T1 AT E458332T1
Authority
AT
Austria
Prior art keywords
circuit arrangement
stage
input stage
connected downstream
operating
Prior art date
Application number
AT05735281T
Other languages
English (en)
Inventor
Nico Berckmans
Ruurd Visser
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE458332T1 publication Critical patent/ATE458332T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40013—Details regarding a bus controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
    • H04L12/4135—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD] using bit-wise arbitration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset
    • H04L25/062—Setting decision thresholds using feedforward techniques only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215—Controller Area Network CAN

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AT05735281T 2004-05-11 2005-05-09 Schaltungsanordnung und verfahren zum betrieb einer solchen schaltungsanordnung ATE458332T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04102025 2004-05-11
PCT/IB2005/051499 WO2005109776A1 (en) 2004-05-11 2005-05-09 Circuit arrangement and method of operating such circuit arrangement

Publications (1)

Publication Number Publication Date
ATE458332T1 true ATE458332T1 (de) 2010-03-15

Family

ID=34966557

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05735281T ATE458332T1 (de) 2004-05-11 2005-05-09 Schaltungsanordnung und verfahren zum betrieb einer solchen schaltungsanordnung

Country Status (7)

Country Link
US (1) US7738566B2 (de)
EP (1) EP1751924B1 (de)
JP (1) JP2007537649A (de)
CN (1) CN100542118C (de)
AT (1) ATE458332T1 (de)
DE (1) DE602005019401D1 (de)
WO (1) WO2005109776A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010043484A1 (de) * 2010-11-05 2012-05-10 Robert Bosch Gmbh Vorrichtung und Verfahren zur seriellen Datenübertragung mit hoher Datenrate
TWI465033B (zh) 2012-04-19 2014-12-11 Ind Tech Res Inst 射頻前端電路及其操作方法
US9965426B2 (en) * 2015-01-07 2018-05-08 Infineon Technologies Ag System and method for a low emission network
TWI594587B (zh) 2015-10-02 2017-08-01 Receive circuit capable of receiving a wide range of common-mode input voltage
CN105281794B (zh) * 2015-10-20 2017-10-31 晶焱科技股份有限公司 可接收超宽共模输入电压范围的接收电路
US10042807B2 (en) * 2016-04-05 2018-08-07 Infineon Technologies Ag Differential bus receiver with four-quadrant input circuit
US10771280B1 (en) * 2019-02-20 2020-09-08 Texas Instruments Incorporated Low-power wake-up circuit for controller area network (CAN) transceiver

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3826774A1 (de) * 1988-08-06 1990-02-08 Bosch Gmbh Robert Netzwerkschnittstelle
DE4108709B4 (de) 1991-03-16 2007-02-22 Robert Bosch Gmbh Empfangskomparator
DE4229175A1 (de) * 1992-09-02 1994-03-03 Bosch Gmbh Robert Netzwerkschnittstelle
DE69425368T2 (de) * 1994-04-15 2000-12-07 Stmicroelectronics S.R.L., Agrate Brianza Schaltung zur Verschiebung des Signalpegels von hohem auf ein niedriges Potential
DE19503460C1 (de) * 1995-02-03 1996-03-07 Daimler Benz Ag Fehlertolerante Endstufe für ein digitales Zweileiterbus-Datenkommunikationssystem
JPH08228142A (ja) * 1995-02-22 1996-09-03 Oki Electric Ind Co Ltd 信号レベルシフト装置
GB9712690D0 (en) * 1997-06-18 1997-08-20 Scimat Ltd Non-woven fabric treatment
US6111431A (en) * 1998-05-14 2000-08-29 National Semiconductor Corporation LVDS driver for backplane applications
JP2002543745A (ja) 1999-04-28 2002-12-17 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Ｃａｎ通信バスからの信号の共通モード成分を抑制する回路
DE10061945A1 (de) * 2000-12-13 2002-07-18 Bosch Gmbh Robert Busschnittstelle und Verfahren zum Ankoppeln eines Busteilnehmers an einen Bus
US7058131B2 (en) * 2001-11-08 2006-06-06 International Business Machines Corporation Signal transmission system with programmable voltage reference
US6674312B2 (en) * 2002-03-15 2004-01-06 Synthesys Differential signal reception device and method for supporting variable threshold levels
US7113759B2 (en) * 2002-08-28 2006-09-26 Texas Instruments Incorporated Controller area network transceiver having capacitive balancing circuit for improved receiver common-mode rejection
CN2618803Y (zh) * 2003-05-08 2004-06-02 安徽工程科技学院 网络化车用仪表机芯电路
CN2652723Y (zh) * 2003-10-13 2004-11-03 东风电动车辆股份有限公司 带can通信的汽车智能仪表系统
US7183896B2 (en) * 2004-01-13 2007-02-27 Temic Automotive Of North America, Inc. Wake-up circuit

Also Published As

Publication number Publication date
EP1751924B1 (de) 2010-02-17
US7738566B2 (en) 2010-06-15
WO2005109776A1 (en) 2005-11-17
EP1751924A1 (de) 2007-02-14
DE602005019401D1 (de) 2010-04-01
CN100542118C (zh) 2009-09-16
US20070217548A1 (en) 2007-09-20
CN1954558A (zh) 2007-04-25
JP2007537649A (ja) 2007-12-20

Similar Documents

Publication Publication Date Title
WO2006088762A3 (en) Distributed supply current switch circuits for enabling individual power domains
WO2007081466A3 (en) System and method for operating components of an integrated circuit at independent frequencies and/or voltages
DE602008004547D1 (de) 12c-bus-schnittstelle mit parallelbetriebsmodus
ATE458332T1 (de) Schaltungsanordnung und verfahren zum betrieb einer solchen schaltungsanordnung
WO2005111800A3 (en) Masking within a data processing system having applicability for a development interface
ATE484791T1 (de) Bit-generator
WO2007112032A3 (en) Fpga routing with reservation for long lines and sharing long lines
DE60031214D1 (de) Spannungsschutzschaltung und -Verfahren für einen Eingangs/Ausgangsanschluss
WO2009085489A3 (en) Method and apparatus for efficient programmable cyclic redundancy check (crc)
ATE392076T1 (de) Vorverzerrungsschema
ATE497315T1 (de) Verfahren und vorrichtungen zur bereitstellung von benetzungsstrom
DE602006002022D1 (de) Verfahren und Vorrichtung zur Datensendung zwischen USB-Kunden
ATE539525T1 (de) Verfahren zum austausch von parametrier- und konfigurierdaten zwischen einem konfigurier- oder managementsystem und einem feldgerät
DE602007011759D1 (de) Für durchgehenden luftstrom konfiguriertes elektronisches modul und system damit
WO2009069043A3 (en) Method of managing data in communication network comprising at least a first and a second node
DE602005006913D1 (de) Schaltungsplatte für Tintenstrahldruckkopf, Verfahren zu ihrer Herstellung, und damit ausgestattetem Tintenstrahldruckkopf
ATE453153T1 (de) Botschaftsverwalter und verfahren zur steuerung des zugriffs auf daten eines botschaftsspeichers eines kommunikationsbausteins
GB201106055D0 (en) Method and apparatus for use in the design and manufacture of integrated circuits
DE502005005287D1 (de) Verfahren und vorrichtung zur erzeugung eines modussignals bei einem rechnersystem mit mehreren komponenten
DE60128403D1 (de) Mittel zur kompensation eines datenabhängigen versorgungsstromes in einer elektronischen schaltung
DE602004022658D1 (de) Verfahren und anordnung mit speicherprotokol zur speicherverbindung
ATE467163T1 (de) Diagnostisches verfahren für betriebsfehler einer funktionele-architektur
ATE415742T1 (de) Datenübertrasgungssystem und -verfahren in einer elektronischen schaltung
DE602006012383D1 (de) Routing-einrichtung für ein unterseeisches elektronikmodul
JP2007537649A5 (de)

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties