ATE459923T1 - Bus-schaltung - Google Patents

Bus-schaltung

Info

Publication number
ATE459923T1
ATE459923T1 AT06796012T AT06796012T ATE459923T1 AT E459923 T1 ATE459923 T1 AT E459923T1 AT 06796012 T AT06796012 T AT 06796012T AT 06796012 T AT06796012 T AT 06796012T AT E459923 T1 ATE459923 T1 AT E459923T1
Authority
AT
Austria
Prior art keywords
circuit
clock
time interval
duration corresponding
integer number
Prior art date
Application number
AT06796012T
Other languages
English (en)
Inventor
Xavier Lambrecht
Vlimmeren Bernardus Van
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE459923T1 publication Critical patent/ATE459923T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
  • Information Transfer Systems (AREA)
  • Amplifiers (AREA)
  • Traffic Control Systems (AREA)
  • Small-Scale Networks (AREA)
  • Platform Screen Doors And Railroad Systems (AREA)
AT06796012T 2005-09-21 2006-09-13 Bus-schaltung ATE459923T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05108725 2005-09-21
PCT/IB2006/053249 WO2007034368A2 (en) 2005-09-21 2006-09-13 Bus circuit

Publications (1)

Publication Number Publication Date
ATE459923T1 true ATE459923T1 (de) 2010-03-15

Family

ID=37889193

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06796012T ATE459923T1 (de) 2005-09-21 2006-09-13 Bus-schaltung

Country Status (8)

Country Link
US (2) US7683692B2 (de)
EP (1) EP1932288B1 (de)
JP (1) JP2009509226A (de)
CN (1) CN101356517B (de)
AT (1) ATE459923T1 (de)
DE (1) DE602006012703D1 (de)
TW (1) TWI407314B (de)
WO (1) WO2007034368A2 (de)

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DE602006012703D1 (de) * 2005-09-21 2010-04-15 Nxp Bv Bus-schaltung
US8520835B2 (en) * 2006-04-18 2013-08-27 2Wire, Inc. Method and apparatus for providing power to a network interface device via telephone lines
US8332572B2 (en) 2008-02-05 2012-12-11 Spansion Llc Wear leveling mechanism using a DRAM buffer
US8327052B2 (en) * 2009-12-23 2012-12-04 Spansion Llc Variable read latency on a serial memory bus
US20120327942A1 (en) * 2011-06-27 2012-12-27 Denso Corporation Communication network system
RU2615771C2 (ru) * 2011-08-23 2017-04-11 Филипс Лайтинг Холдинг Б.В. Система, содержащая главный электрический блок и периферийный электрический блок
US9571155B2 (en) * 2014-08-25 2017-02-14 Samsung Display Co., Ltd. Method of startup sequence for a panel interface
CN106559160A (zh) * 2015-09-30 2017-04-05 阿尔卡特朗讯 具有传播延迟校准功能的时钟接口
US9501439B1 (en) * 2016-01-19 2016-11-22 International Business Machines Corporation Communicating in an integrated circuit using hardware-managed virtual channels
US10652032B2 (en) * 2017-06-20 2020-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Device signature generation
US11030142B2 (en) 2017-06-28 2021-06-08 Intel Corporation Method, apparatus and system for dynamic control of clock signaling on a bus
US11354266B2 (en) * 2020-08-19 2022-06-07 Qualcomm Incorporated Hang correction in a power management interface bus
US11327922B2 (en) * 2020-08-19 2022-05-10 Qualcomm Incorporated Bus ownership for a system power management interface (SPMI) bus
US12130761B2 (en) 2023-02-08 2024-10-29 Qualcomm Incorporated Bus clock line handover systems and methods
CN117093526B (zh) * 2023-10-16 2024-01-30 浙江地芯引力科技有限公司 下拉电阻控制系统、芯片和电子设备
US12475073B2 (en) * 2024-03-10 2025-11-18 Qualcomm Incorporated Multi-command transactions

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WO2000067404A1 (de) * 1999-04-29 2000-11-09 Siemens Aktiengesellschaft Verfahren zur bildung bzw. ermittlung einer signalfolge, verfahren zur synchronisation, sendeeinheit und empfangseinheit
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DE602006012703D1 (de) * 2005-09-21 2010-04-15 Nxp Bv Bus-schaltung
TW200825705A (en) * 2006-04-26 2008-06-16 Nxp Bv Method and system for power-state transition controllers
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Also Published As

Publication number Publication date
US20100189287A1 (en) 2010-07-29
US7683692B2 (en) 2010-03-23
US7872517B2 (en) 2011-01-18
US20090085631A1 (en) 2009-04-02
WO2007034368A3 (en) 2008-08-14
EP1932288B1 (de) 2010-03-03
EP1932288A2 (de) 2008-06-18
CN101356517B (zh) 2010-06-23
JP2009509226A (ja) 2009-03-05
WO2007034368A2 (en) 2007-03-29
TWI407314B (zh) 2013-09-01
TW200811661A (en) 2008-03-01
DE602006012703D1 (de) 2010-04-15
CN101356517A (zh) 2009-01-28

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Legal Events

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