ATE463005T1 - Nur-cache-warteschlangenoption für eine cache- steuerung - Google Patents

Nur-cache-warteschlangenoption für eine cache- steuerung

Info

Publication number
ATE463005T1
ATE463005T1 AT04704037T AT04704037T ATE463005T1 AT E463005 T1 ATE463005 T1 AT E463005T1 AT 04704037 T AT04704037 T AT 04704037T AT 04704037 T AT04704037 T AT 04704037T AT E463005 T1 ATE463005 T1 AT E463005T1
Authority
AT
Austria
Prior art keywords
cache
queue
command
disk
subsystem
Prior art date
Application number
AT04704037T
Other languages
English (en)
Inventor
Alan Cox
Original Assignee
Red Hat Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Red Hat Inc filed Critical Red Hat Inc
Application granted granted Critical
Publication of ATE463005T1 publication Critical patent/ATE463005T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT04704037T 2003-01-21 2004-01-21 Nur-cache-warteschlangenoption für eine cache- steuerung ATE463005T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/348,041 US7024499B2 (en) 2003-01-21 2003-01-21 Cache only queue option for cache controller
PCT/US2004/001465 WO2004066084A2 (en) 2003-01-21 2004-01-21 Cache only queue option for cache controller

Publications (1)

Publication Number Publication Date
ATE463005T1 true ATE463005T1 (de) 2010-04-15

Family

ID=32712463

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04704037T ATE463005T1 (de) 2003-01-21 2004-01-21 Nur-cache-warteschlangenoption für eine cache- steuerung

Country Status (5)

Country Link
US (1) US7024499B2 (de)
EP (1) EP1588246B1 (de)
AT (1) ATE463005T1 (de)
DE (1) DE602004026269D1 (de)
WO (1) WO2004066084A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7162550B2 (en) * 2003-07-21 2007-01-09 Intel Corporation Method, system, and program for managing requests to an Input/Output device
US8245229B2 (en) * 2008-09-30 2012-08-14 Microsoft Corporation Temporal batching of I/O jobs
US8346995B2 (en) 2008-09-30 2013-01-01 Microsoft Corporation Balancing usage of hardware devices among clients
US8479214B2 (en) * 2008-09-30 2013-07-02 Microsoft Corporation Hardware throughput saturation detection

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4425615A (en) * 1980-11-14 1984-01-10 Sperry Corporation Hierarchical memory system having cache/disk subsystem with command queues for plural disks
US6182176B1 (en) * 1994-02-24 2001-01-30 Hewlett-Packard Company Queue-based predictive flow control mechanism
JP2611746B2 (ja) * 1994-12-19 1997-05-21 日本電気株式会社 入出力インタフェース装置及びその制御方法
US5649157A (en) * 1995-03-30 1997-07-15 Hewlett-Packard Co. Memory controller with priority queues
US5815648A (en) * 1995-11-14 1998-09-29 Eccs, Inc. Apparatus and method for changing the cache mode dynamically in a storage array system
US5937205A (en) * 1995-12-06 1999-08-10 International Business Machines Corporation Dynamic queue prioritization by modifying priority value based on queue's level and serving less than a maximum number of requests per queue
US5944838A (en) * 1997-03-31 1999-08-31 Lsi Logic Corporation Method for fast queue restart after redundant I/O path failover
US6311256B2 (en) * 1997-06-30 2001-10-30 Emc Corporation Command insertion and reordering at the same storage controller
US5991825A (en) * 1997-07-11 1999-11-23 International Business Machines Corporation System for handling missed revolution in a disk drive by aborting the execution of primary command and executing secondary command if a missed revolution occurs
US6292856B1 (en) * 1999-01-29 2001-09-18 International Business Machines Corporation System and method for application influence of I/O service order post I/O request
US6564271B2 (en) * 1999-06-09 2003-05-13 Qlogic Corporation Method and apparatus for automatically transferring I/O blocks between a host system and a host adapter
US6834315B2 (en) * 2001-03-26 2004-12-21 International Business Machines Corporation Method, system, and program for prioritizing input/output (I/O) requests submitted to a device driver

Also Published As

Publication number Publication date
WO2004066084A2 (en) 2004-08-05
EP1588246A2 (de) 2005-10-26
EP1588246B1 (de) 2010-03-31
US20040143687A1 (en) 2004-07-22
DE602004026269D1 (de) 2010-05-12
WO2004066084A3 (en) 2004-10-28
US7024499B2 (en) 2006-04-04
EP1588246A4 (de) 2006-06-14

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties