ATE463462T1 - Verfahren zur herstellung von mikrobearbeiteten anordnungen - Google Patents

Verfahren zur herstellung von mikrobearbeiteten anordnungen

Info

Publication number
ATE463462T1
ATE463462T1 AT01870213T AT01870213T ATE463462T1 AT E463462 T1 ATE463462 T1 AT E463462T1 AT 01870213 T AT01870213 T AT 01870213T AT 01870213 T AT01870213 T AT 01870213T AT E463462 T1 ATE463462 T1 AT E463462T1
Authority
AT
Austria
Prior art keywords
wafer
machined
arrangements
plane
cleavage
Prior art date
Application number
AT01870213T
Other languages
English (en)
Inventor
Ann Wivrouw
Vries Atze De
Moor Piet De
Luc Haspelagh
Brigitte Parmentier
Agnes Verbist
Constantine Anagnostopoulos
Original Assignee
Imec
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP00870227A external-priority patent/EP1195352A1/de
Application filed by Imec, Eastman Kodak Co filed Critical Imec
Application granted granted Critical
Publication of ATE463462T1 publication Critical patent/ATE463462T1/de

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388—Etch mask forming
    • B81C1/00404—Mask characterised by its size, orientation or shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Immobilizing And Processing Of Enzymes And Microorganisms (AREA)
AT01870213T 2000-10-09 2001-10-08 Verfahren zur herstellung von mikrobearbeiteten anordnungen ATE463462T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00870227A EP1195352A1 (de) 2000-10-09 2000-10-09 Verfahren zur Herstellung von mikrobearbeiteten Anordnungen und derart hergestellte Anordnungen
US23922600P 2000-10-10 2000-10-10

Publications (1)

Publication Number Publication Date
ATE463462T1 true ATE463462T1 (de) 2010-04-15

Family

ID=26074298

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01870213T ATE463462T1 (de) 2000-10-09 2001-10-08 Verfahren zur herstellung von mikrobearbeiteten anordnungen

Country Status (4)

Country Link
US (1) US6740542B2 (de)
JP (1) JP4128764B2 (de)
AT (1) ATE463462T1 (de)
DE (1) DE60141737D1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004058267A (ja) * 2002-06-03 2004-02-26 Japan Science & Technology Corp シリコン微小細線からなる３次元構造体、その製造方法及びそれを利用した装置
JP4836483B2 (ja) * 2005-04-15 2011-12-14 セイコーインスツル株式会社 半導体装置
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
JP5724342B2 (ja) 2009-12-10 2015-05-27 大日本印刷株式会社 パターン配置方法並びにシリコンウェハ及び半導体デバイスの製造方法
JP6091108B2 (ja) * 2012-08-03 2017-03-08 アズビル株式会社 シリコンチューブの製造方法
JP2014137305A (ja) * 2013-01-17 2014-07-28 Seiko Instruments Inc 変位検知装置及び変位検知装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4278987A (en) * 1977-10-17 1981-07-14 Hitachi, Ltd. Junction isolated IC with thick EPI portion having sides at least 20 degrees from (110) orientations
DE3435138A1 (de) 1984-09-25 1986-04-03 Siemens AG, 1000 Berlin und 8000 München Verbesserung zu einem verfahren zum vereinzeln von halbleiter-bauelementen, die durch brechen aus halbleiter-wafern gewonnen sind
US4969359A (en) * 1989-04-06 1990-11-13 Ford Motor Company Silicon accelerometer responsive to three orthogonal force components and method for fabricating
JPH03219618A (ja) 1990-01-24 1991-09-27 Sony Corp 描画方法と描画装置
US5349211A (en) 1992-03-26 1994-09-20 Nec Corporation Semiconductor infrared emitting device with oblique side surface with respect to the cleavage
DE4342767A1 (de) 1993-12-15 1995-06-22 Ant Nachrichtentech Verfahren zur Herstellung einer quaderförmigen Vertiefung zur Aufnahme eines Bauelementes in einer Trägerplatte
JP3219618B2 (ja) 1994-12-13 2001-10-15 三菱重工業株式会社 タイヤ加硫設備
US6213050B1 (en) * 1998-12-01 2001-04-10 Silicon Genesis Corporation Enhanced plasma mode and computer system for plasma immersion ion implantation
US6245584B1 (en) * 1999-07-01 2001-06-12 Advanced Micro Devices Method for detecting adjustment error in photolithographic stepping printer
US6440616B1 (en) * 1999-09-28 2002-08-27 Kabushiki Kaisha Toshiba Mask and method for focus monitoring

Also Published As

Publication number Publication date
DE60141737D1 (de) 2010-05-20
US6740542B2 (en) 2004-05-25
JP4128764B2 (ja) 2008-07-30
JP2002192498A (ja) 2002-07-10
US20020108926A1 (en) 2002-08-15

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties