ATE464604T1 - Verteilte speichersteuerung und bandbreitenoptimierung - Google Patents

Verteilte speichersteuerung und bandbreitenoptimierung

Info

Publication number
ATE464604T1
ATE464604T1 AT00993654T AT00993654T ATE464604T1 AT E464604 T1 ATE464604 T1 AT E464604T1 AT 00993654 T AT00993654 T AT 00993654T AT 00993654 T AT00993654 T AT 00993654T AT E464604 T1 ATE464604 T1 AT E464604T1
Authority
AT
Austria
Prior art keywords
memory
storage control
distributed storage
bandwidth optimization
control logic
Prior art date
Application number
AT00993654T
Other languages
English (en)
Inventor
Gilbert Wolrich
Debra Bernstein
Matthew Adiletta
William Wheeler
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE464604T1 publication Critical patent/ATE464604T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT00993654T 1999-12-28 2000-12-06 Verteilte speichersteuerung und bandbreitenoptimierung ATE464604T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/473,112 US6560667B1 (en) 1999-12-28 1999-12-28 Handling contiguous memory references in a multi-queue system
PCT/US2000/042663 WO2001048619A2 (en) 1999-12-28 2000-12-06 Distributed memory control and bandwidth optimization

Publications (1)

Publication Number Publication Date
ATE464604T1 true ATE464604T1 (de) 2010-04-15

Family

ID=23878258

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00993654T ATE464604T1 (de) 1999-12-28 2000-12-06 Verteilte speichersteuerung und bandbreitenoptimierung

Country Status (8)

Country Link
US (1) US6560667B1 (de)
EP (1) EP1282862B1 (de)
CN (1) CN1238793C (de)
AT (1) ATE464604T1 (de)
AU (1) AU5788001A (de)
DE (1) DE60044209D1 (de)
TW (1) TWI229259B (de)
WO (1) WO2001048619A2 (de)

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Also Published As

Publication number Publication date
CN1437730A (zh) 2003-08-20
EP1282862B1 (de) 2010-04-14
WO2001048619A3 (en) 2002-11-14
AU5788001A (en) 2001-07-09
HK1051241A1 (en) 2003-07-25
CN1238793C (zh) 2006-01-25
TWI229259B (en) 2005-03-11
WO2001048619A2 (en) 2001-07-05
US6560667B1 (en) 2003-05-06
EP1282862A2 (de) 2003-02-12
DE60044209D1 (de) 2010-05-27

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