ATE464607T1 - Verfahren und gerät zum bewirken einer verbindung von variabler breite - Google Patents

Verfahren und gerät zum bewirken einer verbindung von variabler breite

Info

Publication number
ATE464607T1
ATE464607T1 AT04257160T AT04257160T ATE464607T1 AT E464607 T1 ATE464607 T1 AT E464607T1 AT 04257160 T AT04257160 T AT 04257160T AT 04257160 T AT04257160 T AT 04257160T AT E464607 T1 ATE464607 T1 AT E464607T1
Authority
AT
Austria
Prior art keywords
effecting
variable width
width joint
joint
swizzled
Prior art date
Application number
AT04257160T
Other languages
English (en)
Inventor
Maurice B Steinman
Naveen Cherukuri
Aaron T Spink
Allen J Baum
Sanjay Dabral
Tim Frodsham
Rahul R Shah
Davis S Dunning
Theodore Z Schoenborn
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE464607T1 publication Critical patent/ATE464607T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Processing Of Terminals (AREA)
  • Vehicle Body Suspensions (AREA)
AT04257160T 2004-05-21 2004-11-18 Verfahren und gerät zum bewirken einer verbindung von variabler breite ATE464607T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/850,809 US7957428B2 (en) 2004-05-21 2004-05-21 Methods and apparatuses to effect a variable-width link

Publications (1)

Publication Number Publication Date
ATE464607T1 true ATE464607T1 (de) 2010-04-15

Family

ID=34930811

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04257160T ATE464607T1 (de) 2004-05-21 2004-11-18 Verfahren und gerät zum bewirken einer verbindung von variabler breite

Country Status (8)

Country Link
US (2) US7957428B2 (de)
EP (1) EP1598745B1 (de)
JP (1) JP4035532B2 (de)
CN (2) CN1700700A (de)
AT (1) ATE464607T1 (de)
DE (1) DE602004026555D1 (de)
RU (1) RU2288542C2 (de)
TW (1) TWI311252B (de)

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US9479196B2 (en) * 2012-10-22 2016-10-25 Intel Corporation High performance interconnect link layer
KR101691756B1 (ko) 2012-10-22 2016-12-30 인텔 코포레이션 코히어런스 프로토콜 테이블
US9280507B2 (en) 2012-10-22 2016-03-08 Intel Corporation High performance interconnect physical layer
US9009540B2 (en) 2012-12-05 2015-04-14 Intel Corporation Memory subsystem command bus stress testing
US9009531B2 (en) 2012-12-05 2015-04-14 Intel Corporation Memory subsystem data bus stress testing
JP6321194B2 (ja) 2014-03-20 2018-05-09 インテル コーポレイション リンクインタフェースの使用されていないハードウェアの電力消費を制御するための方法、装置及びシステム
US9552253B2 (en) * 2014-09-24 2017-01-24 Intel Corporation Probabilistic flit error checking
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Also Published As

Publication number Publication date
TW200538944A (en) 2005-12-01
EP1598745B1 (de) 2010-04-14
JP4035532B2 (ja) 2008-01-23
RU2004130346A (ru) 2006-03-20
EP1598745A2 (de) 2005-11-23
US7957428B2 (en) 2011-06-07
CN1700700A (zh) 2005-11-23
EP1598745A3 (de) 2006-11-02
JP2005332359A (ja) 2005-12-02
CN103034605A (zh) 2013-04-10
US20050259696A1 (en) 2005-11-24
CN103034605B (zh) 2016-08-17
US8204067B2 (en) 2012-06-19
TWI311252B (en) 2009-06-21
US20050259599A1 (en) 2005-11-24
DE602004026555D1 (de) 2010-05-27
RU2288542C2 (ru) 2006-11-27

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