ATE470896T1 - Transaktionstapel für elektronische geräte mit einem nichtflüchtigen speicher, der eine begrenzte anzahl von schreibzyklen aufweist - Google Patents

Transaktionstapel für elektronische geräte mit einem nichtflüchtigen speicher, der eine begrenzte anzahl von schreibzyklen aufweist

Info

Publication number
ATE470896T1
ATE470896T1 AT05425277T AT05425277T ATE470896T1 AT E470896 T1 ATE470896 T1 AT E470896T1 AT 05425277 T AT05425277 T AT 05425277T AT 05425277 T AT05425277 T AT 05425277T AT E470896 T1 ATE470896 T1 AT E470896T1
Authority
AT
Austria
Prior art keywords
transaction
buffer
stack
volatile memory
electronic devices
Prior art date
Application number
AT05425277T
Other languages
English (en)
Inventor
Mariano Concilio
Original Assignee
Incard Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=35044911&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE470896(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Incard Sa filed Critical Incard Sa
Application granted granted Critical
Publication of ATE470896T1 publication Critical patent/ATE470896T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT05425277T 2005-04-29 2005-04-29 Transaktionstapel für elektronische geräte mit einem nichtflüchtigen speicher, der eine begrenzte anzahl von schreibzyklen aufweist ATE470896T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP05425277A EP1717665B1 (de) 2005-04-29 2005-04-29 Transaktionstapel für elektronische Geräte mit einem nichtflüchtigen Speicher, der eine begrenzte Anzahl von Schreibzyklen aufweist

Publications (1)

Publication Number Publication Date
ATE470896T1 true ATE470896T1 (de) 2010-06-15

Family

ID=35044911

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05425277T ATE470896T1 (de) 2005-04-29 2005-04-29 Transaktionstapel für elektronische geräte mit einem nichtflüchtigen speicher, der eine begrenzte anzahl von schreibzyklen aufweist

Country Status (8)

Country Link
US (1) US7861016B2 (de)
EP (1) EP1717665B1 (de)
AT (1) ATE470896T1 (de)
BR (1) BRPI0611161A2 (de)
DE (1) DE602005021753D1 (de)
ES (1) ES2349953T3 (de)
PT (1) PT1717665E (de)
WO (1) WO2006117146A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10846279B2 (en) 2015-01-29 2020-11-24 Hewlett Packard Enterprise Development Lp Transactional key-value store
KR102570367B1 (ko) * 2016-04-21 2023-08-28 삼성전자주식회사 불휘발성 메모리 장치 및 컨트롤러를 포함하는 스토리지 장치를 액세스하는 액세스 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5003471A (en) * 1988-09-01 1991-03-26 Gibson Glenn A Windowed programmable data transferring apparatus which uses a selective number of address offset registers and synchronizes memory access to buffer
DE69817543T2 (de) * 1998-06-08 2004-06-24 International Business Machines Corp. Automatische Datenrückgewinnung in Chipkarten
US6862651B2 (en) * 2000-12-20 2005-03-01 Microsoft Corporation Automotive computing devices with emergency power shut down capabilities
US7325082B1 (en) * 2004-08-25 2008-01-29 Unisys Corporation System and method for guaranteeing transactional fairness among multiple requesters

Also Published As

Publication number Publication date
WO2006117146A3 (en) 2007-01-18
US20080195773A1 (en) 2008-08-14
BRPI0611161A2 (pt) 2019-02-26
ES2349953T3 (es) 2011-01-13
PT1717665E (pt) 2010-10-06
WO2006117146A2 (en) 2006-11-09
EP1717665A1 (de) 2006-11-02
EP1717665B1 (de) 2010-06-09
US7861016B2 (en) 2010-12-28
DE602005021753D1 (de) 2010-07-22

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