ATE475986T1 - Verfahren zum herstellen eines halbleiterbauelements - Google Patents

Verfahren zum herstellen eines halbleiterbauelements

Info

Publication number
ATE475986T1
ATE475986T1 AT05702944T AT05702944T ATE475986T1 AT E475986 T1 ATE475986 T1 AT E475986T1 AT 05702944 T AT05702944 T AT 05702944T AT 05702944 T AT05702944 T AT 05702944T AT E475986 T1 ATE475986 T1 AT E475986T1
Authority
AT
Austria
Prior art keywords
drain
source
extensions
semiconductor device
active layer
Prior art date
Application number
AT05702944T
Other languages
English (en)
Inventor
Radu Surdeanu
Gerben Doornbos
Dal Marcus Van
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE475986T1 publication Critical patent/ATE475986T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H10D30/0229—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET forming drain regions and lightly-doped drain [LDD] simultaneously, e.g. using implantation through a T-shaped mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
AT05702944T 2004-02-19 2005-02-10 Verfahren zum herstellen eines halbleiterbauelements ATE475986T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04100653 2004-02-19
PCT/IB2005/050527 WO2005083769A1 (en) 2004-02-19 2005-02-10 Semiconductor device and method of manufacturing a semiconductor device

Publications (1)

Publication Number Publication Date
ATE475986T1 true ATE475986T1 (de) 2010-08-15

Family

ID=34896086

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05702944T ATE475986T1 (de) 2004-02-19 2005-02-10 Verfahren zum herstellen eines halbleiterbauelements

Country Status (7)

Country Link
US (1) US20080150024A1 (de)
EP (1) EP1719164B1 (de)
JP (1) JP2007524242A (de)
CN (1) CN1922719B (de)
AT (1) ATE475986T1 (de)
DE (1) DE602005022561D1 (de)
WO (1) WO2005083769A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7569888B2 (en) * 2005-08-10 2009-08-04 Toshiba America Electronic Components, Inc. Semiconductor device with close stress liner film and method of manufacturing the same
JP2008198763A (ja) * 2007-02-13 2008-08-28 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP4503627B2 (ja) * 2007-03-29 2010-07-14 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
DE102008030854B4 (de) * 2008-06-30 2014-03-20 Advanced Micro Devices, Inc. MOS-Transistoren mit abgesenkten Drain- und Source-Bereichen und nicht-konformen Metallsilizidgebieten und Verfahren zum Herstellen der Transistoren
JP2011029610A (ja) * 2009-06-26 2011-02-10 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
JP5659098B2 (ja) * 2011-07-19 2015-01-28 株式会社東芝 半導体装置の製造方法
CN103531468B (zh) * 2012-07-02 2018-05-08 中芯国际集成电路制造(上海)有限公司 一种mos晶体管及其制作方法
US9269626B2 (en) * 2014-02-06 2016-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure and method for manufacturing thereof
CN105633087B (zh) * 2014-11-03 2018-10-12 旺宏电子股份有限公司 半导体元件及其制造方法
US9685535B1 (en) 2016-09-09 2017-06-20 International Business Machines Corporation Conductive contacts in semiconductor on insulator substrate
FR3069374B1 (fr) 2017-07-21 2020-01-17 Stmicroelectronics (Rousset) Sas Transistor mos a effet bosse reduit
FR3069376B1 (fr) 2017-07-21 2020-07-03 Stmicroelectronics (Rousset) Sas Transistor comprenant une grille elargie
FR3069377B1 (fr) 2017-07-21 2020-07-03 Stmicroelectronics (Rousset) Sas Transistor mos a double blocs de grille a tension de claquage augmentee
FR3143839A1 (fr) * 2022-12-20 2024-06-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Realisation d’un transistor a source et de drain siliciurees proches du canal

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204132B1 (en) * 1998-05-06 2001-03-20 Texas Instruments Incorporated Method of forming a silicide layer using an angled pre-amorphization implant
US6180472B1 (en) * 1998-07-28 2001-01-30 Matsushita Electrons Corporation Method for fabricating semiconductor device
US6242776B1 (en) * 1999-06-02 2001-06-05 Advanced Micro Devices, Inc. Device improvement by lowering LDD resistance with new silicide process
KR100327347B1 (en) * 2000-07-22 2002-03-06 Samsung Electronics Co Ltd Metal oxide semiconductor field effect transistor having reduced resistance between source and drain and fabricating method thereof
US6380057B1 (en) * 2001-02-13 2002-04-30 Advanced Micro Devices, Inc. Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant
US20020137268A1 (en) * 2001-03-20 2002-09-26 Pellerin John G. Method of forming silicide contacts and device incorporation same
WO2002082503A2 (en) * 2001-04-02 2002-10-17 Advanced Micro Devices, Inc. Multi-thickness silicide device
US6441433B1 (en) * 2001-04-02 2002-08-27 Advanced Micro Devices, Inc. Method of making a multi-thickness silicide SOI device
US6888198B1 (en) * 2001-06-04 2005-05-03 Advanced Micro Devices, Inc. Straddled gate FDSOI device
US6465847B1 (en) * 2001-06-11 2002-10-15 Advanced Micro Devices, Inc. Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions
US20040188765A1 (en) * 2003-03-28 2004-09-30 International Business Machines Corporation Cmos device integration for low external resistance
US6946350B2 (en) * 2003-12-31 2005-09-20 Intel Corporation Controlled faceting of source/drain regions

Also Published As

Publication number Publication date
US20080150024A1 (en) 2008-06-26
JP2007524242A (ja) 2007-08-23
EP1719164A1 (de) 2006-11-08
EP1719164B1 (de) 2010-07-28
DE602005022561D1 (de) 2010-09-09
CN1922719B (zh) 2011-05-04
WO2005083769A1 (en) 2005-09-09
CN1922719A (zh) 2007-02-28

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