ATE479943T1 - Verfahren und vorrichtungen zur dynamischen verwaltung von bank-speicher - Google Patents

Verfahren und vorrichtungen zur dynamischen verwaltung von bank-speicher

Info

Publication number
ATE479943T1
ATE479943T1 AT06718933T AT06718933T ATE479943T1 AT E479943 T1 ATE479943 T1 AT E479943T1 AT 06718933 T AT06718933 T AT 06718933T AT 06718933 T AT06718933 T AT 06718933T AT E479943 T1 ATE479943 T1 AT E479943T1
Authority
AT
Austria
Prior art keywords
bank
cache
configuration
memory
banks
Prior art date
Application number
AT06718933T
Other languages
English (en)
Inventor
Thomas Philip Speier
James Norris Dieffenderfer
Ravi Rajagopalan
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE479943T1 publication Critical patent/ATE479943T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Underground Structures, Protecting, Testing And Restoring Foundations (AREA)
AT06718933T 2005-01-21 2006-01-20 Verfahren und vorrichtungen zur dynamischen verwaltung von bank-speicher ATE479943T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/040,600 US8443162B2 (en) 2005-01-21 2005-01-21 Methods and apparatus for dynamically managing banked memory
PCT/US2006/001934 WO2006078837A2 (en) 2005-01-21 2006-01-20 Methods and apparatus for dynamically managing banked memory

Publications (1)

Publication Number Publication Date
ATE479943T1 true ATE479943T1 (de) 2010-09-15

Family

ID=36423520

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06718933T ATE479943T1 (de) 2005-01-21 2006-01-20 Verfahren und vorrichtungen zur dynamischen verwaltung von bank-speicher

Country Status (11)

Country Link
US (1) US8443162B2 (de)
EP (1) EP1849081B1 (de)
JP (1) JP4173192B2 (de)
KR (1) KR100890123B1 (de)
CN (1) CN101137968A (de)
AT (1) ATE479943T1 (de)
DE (1) DE602006016558D1 (de)
IL (1) IL184683A0 (de)
MX (1) MX2007008823A (de)
TW (1) TW200702992A (de)
WO (1) WO2006078837A2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7653070B2 (en) * 2005-06-07 2010-01-26 Broadcom Corporation Method and system for supporting efficient and cache-friendly TCP session lookup operations based on canonicalization tags
US7861055B2 (en) * 2005-06-07 2010-12-28 Broadcom Corporation Method and system for on-chip configurable data ram for fast memory and pseudo associative caches
JP2008234074A (ja) * 2007-03-16 2008-10-02 Fujitsu Ltd キャッシュ装置
US8407399B2 (en) * 2008-10-29 2013-03-26 Sandisk Il Ltd. Method and apparatus for enforcing a flash memory caching policy
US20120303897A1 (en) * 2011-05-28 2012-11-29 Sakthivel Komarasamy Pullagoundapatti Configurable set associative cache way architecture
US8843709B2 (en) * 2011-11-28 2014-09-23 Mediatek Inc. Method and apparatus for performing dynamic configuration
FR2985825B1 (fr) 2012-01-13 2014-12-05 Commissariat Energie Atomique Systeme et procede de gestion de correspondance entre une memoire cache et une memoire principale
US9734079B2 (en) * 2013-06-28 2017-08-15 Intel Corporation Hybrid exclusive multi-level memory architecture with memory management
US9465735B2 (en) * 2013-10-03 2016-10-11 Qualcomm Incorporated System and method for uniform interleaving of data across a multiple-channel memory architecture with asymmetric storage capacity
KR102219288B1 (ko) * 2013-12-09 2021-02-23 삼성전자 주식회사 캐시 모드 및 메모리 모드 동작을 지원하는 메모리 장치 및 이의 동작 방법
US9355038B2 (en) * 2014-09-11 2016-05-31 Qualcomm Incorporated Cache bank spreading for compression algorithms
US9720827B2 (en) * 2014-11-14 2017-08-01 Intel Corporation Providing multiple memory modes for a processor including internal memory
JP6832441B2 (ja) 2017-01-31 2021-02-24 ヒューレット−パッカード デベロップメント カンパニー エル．ピー．Ｈｅｗｌｅｔｔ‐Ｐａｃｋａｒｄ Ｄｅｖｅｌｏｐｍｅｎｔ Ｃｏｍｐａｎｙ， Ｌ．Ｐ． メモリバンク内のメモリユニットに対するアクセス
US11106584B2 (en) * 2019-05-24 2021-08-31 Texas Instmments Incorporated Hardware coherence for memory controller
US11908523B2 (en) * 2021-09-01 2024-02-20 Micron Technology, Inc. Express programming using advanced cache register release in a memory sub-system

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410669A (en) 1993-04-05 1995-04-25 Motorola, Inc. Data processor having a cache memory capable of being used as a linear ram bank
US5854761A (en) * 1997-06-26 1998-12-29 Sun Microsystems, Inc. Cache memory array which stores two-way set associative data
US6108745A (en) * 1997-10-31 2000-08-22 Hewlett-Packard Company Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes
US6226728B1 (en) 1998-04-21 2001-05-01 Intel Corporation Dynamic allocation for efficient management of variable sized data within a nonvolatile memory
US6038673A (en) 1998-11-03 2000-03-14 Intel Corporation Computer system with power management scheme for DRAM devices
US6606686B1 (en) * 1999-07-15 2003-08-12 Texas Instruments Incorporated Unified memory system architecture including cache and directly addressable static random access memory
EP1157336B1 (de) 1999-12-17 2009-07-29 Nxp B.V. Datenprozessor mit cachespeicher
US6532185B2 (en) 2001-02-23 2003-03-11 International Business Machines Corporation Distribution of bank accesses in a multiple bank DRAM used as a data buffer
US7020762B2 (en) 2002-12-24 2006-03-28 Intel Corporation Method and apparatus for determining a dynamic random access memory page management implementation
US7643632B2 (en) * 2004-02-25 2010-01-05 Ternarylogic Llc Ternary and multi-value digital signal scramblers, descramblers and sequence generators

Also Published As

Publication number Publication date
KR100890123B1 (ko) 2009-03-24
MX2007008823A (es) 2007-09-07
EP1849081B1 (de) 2010-09-01
US20060168390A1 (en) 2006-07-27
TW200702992A (en) 2007-01-16
JP2008529132A (ja) 2008-07-31
WO2006078837A2 (en) 2006-07-27
CN101137968A (zh) 2008-03-05
US8443162B2 (en) 2013-05-14
IL184683A0 (en) 2007-12-03
EP1849081A2 (de) 2007-10-31
KR20070101340A (ko) 2007-10-16
WO2006078837A3 (en) 2006-10-12
JP4173192B2 (ja) 2008-10-29
DE602006016558D1 (de) 2010-10-14

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Legal Events

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