ATE48205T1 - Verfahren zum herstellen eines in einem gehaeuse montierten ic-plaettchens. - Google Patents

Verfahren zum herstellen eines in einem gehaeuse montierten ic-plaettchens.

Info

Publication number
ATE48205T1
ATE48205T1 AT85104319T AT85104319T ATE48205T1 AT E48205 T1 ATE48205 T1 AT E48205T1 AT 85104319 T AT85104319 T AT 85104319T AT 85104319 T AT85104319 T AT 85104319T AT E48205 T1 ATE48205 T1 AT E48205T1
Authority
AT
Austria
Prior art keywords
housing
making
chip
water mounted
lead frame
Prior art date
Application number
AT85104319T
Other languages
English (en)
Inventor
Thomas G Gilder Jr
Raymond D O'dean
Original Assignee
Gte Prod Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gte Prod Corp filed Critical Gte Prod Corp
Application granted granted Critical
Publication of ATE48205T1 publication Critical patent/ATE48205T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
AT85104319T 1984-05-02 1985-04-10 Verfahren zum herstellen eines in einem gehaeuse montierten ic-plaettchens. ATE48205T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60631184A 1984-05-02 1984-05-02
EP85104319A EP0163077B1 (de) 1984-05-02 1985-04-10 Verfahren zum Herstellen eines in einem Gehäuse montierten IC-Plättchens

Publications (1)

Publication Number Publication Date
ATE48205T1 true ATE48205T1 (de) 1989-12-15

Family

ID=24427463

Family Applications (1)

Application Number Title Priority Date Filing Date
AT85104319T ATE48205T1 (de) 1984-05-02 1985-04-10 Verfahren zum herstellen eines in einem gehaeuse montierten ic-plaettchens.

Country Status (6)

Country Link
EP (1) EP0163077B1 (de)
JP (1) JPS60240134A (de)
KR (1) KR850008560A (de)
AT (1) ATE48205T1 (de)
CA (1) CA1234926A (de)
DE (1) DE3574433D1 (de)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4137546A (en) * 1977-10-14 1979-01-30 Plessey Incorporated Stamped lead frame for semiconductor packages
FR2462024A1 (fr) * 1979-07-17 1981-02-06 Thomson Csf Plate-forme support de grille de connexion, notamment pour boitier de circuits integres, et boitier comportant une telle plate-forme
US4289922A (en) * 1979-09-04 1981-09-15 Plessey Incorporated Integrated circuit package and lead frame

Also Published As

Publication number Publication date
EP0163077A1 (de) 1985-12-04
CA1234926A (en) 1988-04-05
KR850008560A (ko) 1985-12-18
EP0163077B1 (de) 1989-11-23
DE3574433D1 (en) 1989-12-28
JPS60240134A (ja) 1985-11-29

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee