ATE485527T1 - System und rechnerprogrammprodukt zum testen einer logischen schaltung - Google Patents

System und rechnerprogrammprodukt zum testen einer logischen schaltung

Info

Publication number
ATE485527T1
ATE485527T1 AT07713151T AT07713151T ATE485527T1 AT E485527 T1 ATE485527 T1 AT E485527T1 AT 07713151 T AT07713151 T AT 07713151T AT 07713151 T AT07713151 T AT 07713151T AT E485527 T1 ATE485527 T1 AT E485527T1
Authority
AT
Austria
Prior art keywords
test
logic circuit
self
routine
module
Prior art date
Application number
AT07713151T
Other languages
English (en)
Inventor
Oleksandr Sakada
Florian Bogenberger
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Application granted granted Critical
Publication of ATE485527T1 publication Critical patent/ATE485527T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/005—Testing of electric installations on transport means
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/005—Testing of electric installations on transport means
    • G01R31/006—Testing of electric installations on transport means on road vehicles, e.g. automobiles or trucks
    • G01R31/007—Testing of electric installations on transport means on road vehicles, e.g. automobiles or trucks using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3187—Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Combustion & Propulsion (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Hardware Redundancy (AREA)
  • Tests Of Electronic Circuits (AREA)
AT07713151T 2007-02-16 2007-02-16 System und rechnerprogrammprodukt zum testen einer logischen schaltung ATE485527T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2007/050518 WO2008099239A1 (en) 2007-02-16 2007-02-16 System, computer program product and method for testing a logic circuit

Publications (1)

Publication Number Publication Date
ATE485527T1 true ATE485527T1 (de) 2010-11-15

Family

ID=38596818

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07713151T ATE485527T1 (de) 2007-02-16 2007-02-16 System und rechnerprogrammprodukt zum testen einer logischen schaltung

Country Status (5)

Country Link
US (1) US8286043B2 (de)
EP (1) EP2113087B1 (de)
AT (1) ATE485527T1 (de)
DE (1) DE602007010039D1 (de)
WO (1) WO2008099239A1 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7546501B2 (en) 2006-09-13 2009-06-09 Texas Instruments Incorporated Selecting test circuitry from header signals on power lead
WO2009090502A1 (en) 2008-01-16 2009-07-23 Freescale Semiconductor, Inc. Processor based system having ecc based check and access validation information means
CN102143523B (zh) * 2010-11-18 2014-06-25 华为技术有限公司 基于业务递送平台的应用测试方法和业务递送平台
KR102097988B1 (ko) * 2014-04-09 2020-05-29 한국전자통신연구원 에러 시뮬레이션 장치 및 그 방법
WO2016020477A1 (en) * 2014-08-07 2016-02-11 Osr Enterprises Ag Device, system and method for automated installation and operating environment configuration of a computer system
JP6864992B2 (ja) * 2016-04-28 2021-04-28 日立Astemo株式会社 車両制御システム検証装置及び車両制御システム
KR102627585B1 (ko) * 2016-05-27 2024-01-25 삼성전자주식회사 부 채널 분석 공격을 방지하기 위한 암호화/복호화 연산을 수행하는 전자 회로 및 그것을 포함하는 전자 장치
US10891396B2 (en) * 2016-05-27 2021-01-12 Samsung Electronics Co., Ltd. Electronic circuit performing encryption/decryption operation to prevent side- channel analysis attack, and electronic device including the same
US11686767B2 (en) * 2017-11-02 2023-06-27 Intel Corporation System, apparatus and method for functional testing of one or more fabrics of a processor
US10816595B2 (en) * 2018-10-19 2020-10-27 Nxp Usa, Inc. Self-test apparatuses having distributed self-test controller circuits and controller circuitry to control self-test execution based on self-test properties and method thereof

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DE1282041B (de) * 1960-01-23 1968-11-07 Demag Ag Innenauskleidung fuer Konverterkamine
US6070252A (en) * 1994-09-30 2000-05-30 Intel Corporation Method and apparatus for interactive built-in-self-testing with user-programmable test patterns
US5539878A (en) * 1995-06-16 1996-07-23 Elonex Technologies, Inc. Parallel testing of CPU cache and instruction units
US20020071325A1 (en) * 1996-04-30 2002-06-13 Hii Kuong Hua Built-in self-test arrangement for integrated circuit memory devices
US5963566A (en) * 1996-12-18 1999-10-05 Lsi Logic Corporation Application specific integrated circuit chip and method of testing same
JP2000011691A (ja) * 1998-06-16 2000-01-14 Mitsubishi Electric Corp 半導体試験装置
DE19835258B4 (de) * 1998-08-04 2006-07-27 Infineon Technologies Ag Integrierte dynamische Speicherschaltung mit einer Selbsttesteinrichtung
US6560740B1 (en) * 1999-08-03 2003-05-06 Advanced Micro Devices, Inc. Apparatus and method for programmable built-in self-test and self-repair of embedded memory
US7418642B2 (en) * 2001-07-30 2008-08-26 Marvell International Technology Ltd. Built-in-self-test using embedded memory and processor in an application specific integrated circuit
US7089456B2 (en) * 2002-06-03 2006-08-08 Honeywell International, Inc Error response test system and method using test mask variable
CN100462731C (zh) * 2003-06-09 2009-02-18 爱德万测试株式会社 图案产生器以及测试装置
JP4601305B2 (ja) * 2004-02-27 2010-12-22 富士通セミコンダクター株式会社 半導体装置
US7231621B1 (en) * 2004-04-30 2007-06-12 Xilinx, Inc. Speed verification of an embedded processor in a programmable logic device
US7213182B2 (en) * 2005-01-19 2007-05-01 Advantest Corporation Test apparatus and test method
US8499208B2 (en) * 2006-10-27 2013-07-30 Qualcomm Incorporated Method and apparatus for scheduling BIST routines

Also Published As

Publication number Publication date
US8286043B2 (en) 2012-10-09
WO2008099239A1 (en) 2008-08-21
DE602007010039D1 (de) 2010-12-02
US20100107025A1 (en) 2010-04-29
EP2113087A1 (de) 2009-11-04
EP2113087B1 (de) 2010-10-20

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