ATE485564T1 - System und verfahren zur verwendung einer modellanalyse zum erzeugen gerichteter prüfvektoren - Google Patents

System und verfahren zur verwendung einer modellanalyse zum erzeugen gerichteter prüfvektoren

Info

Publication number
ATE485564T1
ATE485564T1 AT06774341T AT06774341T ATE485564T1 AT E485564 T1 ATE485564 T1 AT E485564T1 AT 06774341 T AT06774341 T AT 06774341T AT 06774341 T AT06774341 T AT 06774341T AT E485564 T1 ATE485564 T1 AT E485564T1
Authority
AT
Austria
Prior art keywords
real
test vectors
system model
model analysis
world
Prior art date
Application number
AT06774341T
Other languages
English (en)
Inventor
Thomas Gaudette
Original Assignee
Mathworks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mathworks Inc filed Critical Mathworks Inc
Application granted granted Critical
Publication of ATE485564T1 publication Critical patent/ATE485564T1/de

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Image Generation (AREA)
  • Eye Examination Apparatus (AREA)
AT06774341T 2005-06-30 2006-06-30 System und verfahren zur verwendung einer modellanalyse zum erzeugen gerichteter prüfvektoren ATE485564T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/173,977 US7970594B2 (en) 2005-06-30 2005-06-30 System and method for using model analysis to generate directed test vectors
PCT/US2006/025539 WO2007005586A1 (en) 2005-06-30 2006-06-30 System and method for using model analysis to generate directed test vectors

Publications (1)

Publication Number Publication Date
ATE485564T1 true ATE485564T1 (de) 2010-11-15

Family

ID=37309245

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06774341T ATE485564T1 (de) 2005-06-30 2006-06-30 System und verfahren zur verwendung einer modellanalyse zum erzeugen gerichteter prüfvektoren

Country Status (5)

Country Link
US (2) US7970594B2 (de)
EP (1) EP1899876B1 (de)
AT (1) ATE485564T1 (de)
DE (1) DE602006017698D1 (de)
WO (1) WO2007005586A1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2153581B1 (de) 2007-06-05 2013-07-31 Astrium Limited Fernprüfsystem und verfahren
US8726241B1 (en) * 2007-06-06 2014-05-13 Rockwell Collins, Inc. Method and system for the development of high-assurance computing elements
DE202007013822U1 (de) * 2007-10-02 2009-02-19 Mann+Hummel Gmbh Filterelement und Filtersystem
US8868400B2 (en) * 2008-04-30 2014-10-21 Netapp, Inc. Modeling storage environments
US8522215B1 (en) 2008-07-14 2013-08-27 The Mathworks, Inc. Coverage analysis for variable size signals
US8612938B2 (en) * 2009-01-05 2013-12-17 Tata Consultancy Services Limited System and method for automatic generation of test data to satisfy modified condition decision coverage
JP5527503B2 (ja) * 2009-02-13 2014-06-18 富士ゼロックス株式会社 監視装置および情報処理システムおよびプログラム
US10365897B1 (en) 2012-05-23 2019-07-30 The Mathworks, Inc. Model ring component
US8230261B2 (en) * 2009-12-17 2012-07-24 Hewlett-Packard Development Company, L.P. Field replaceable unit acquittal policy
US8839214B2 (en) * 2010-06-30 2014-09-16 Microsoft Corporation Indexable type transformations
CN102096410B (zh) * 2010-12-24 2012-06-20 清华大学 一种高速列车运行控制系统功能的动态测试方法
CN102109848A (zh) * 2010-12-24 2011-06-29 清华大学 一种高速列车运行控制系统的可靠性增长测试方法
US9971676B2 (en) 2012-08-30 2018-05-15 Toyota Motor Engineering & Manufacturing North America, Inc. Systems and methods for state based test case generation for software validation
US9727446B2 (en) * 2012-12-05 2017-08-08 The Mathworks, Inc. Modifiers that customize presentation of tested values to constraints
CN103885851B (zh) * 2013-03-01 2017-02-15 上海富欣智能交通控制有限公司 实时功能完整性检查系统
US9146838B2 (en) * 2013-06-03 2015-09-29 The Mathworks, Inc. Code and model coverage as a time series
EP3088069B1 (de) * 2013-12-27 2023-08-02 Toray Industries, Inc. Hohlfasermembranmodul
US10429437B2 (en) * 2015-05-28 2019-10-01 Keysight Technologies, Inc. Automatically generated test diagram
CN110709822B (zh) * 2017-10-13 2021-10-22 华为技术有限公司 一种终端设备的故障处理方法及终端设备
US10915683B2 (en) * 2018-03-08 2021-02-09 Synopsys, Inc. Methodology to create constraints and leverage formal coverage analyzer to achieve faster code coverage closure for an electronic structure
US11379352B1 (en) 2020-12-15 2022-07-05 International Business Machines Corporation System testing infrastructure with hidden variable, hidden attribute, and hidden value detection
US11204848B1 (en) 2020-12-15 2021-12-21 International Business Machines Corporation System testing infrastructure with hidden variable, hidden attribute, and hidden value detection
US11113167B1 (en) 2020-12-15 2021-09-07 International Business Machines Corporation System testing infrastructure with hidden variable, hidden attribute, and hidden value detection
US11132273B1 (en) 2020-12-15 2021-09-28 International Business Machines Corporation System testing infrastructure with hidden variable, hidden attribute, and hidden value detection
US11188453B1 (en) 2020-12-15 2021-11-30 International Business Machines Corporation Verification of software test quality using hidden variables
US11785015B2 (en) 2021-02-24 2023-10-10 Bank Of America Corporation Information security system for detecting unauthorized access requests

Family Cites Families (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320509A (en) * 1979-10-19 1982-03-16 Bell Telephone Laboratories, Incorporated LSI Circuit logic structure including data compression circuitry
US4937765A (en) * 1988-07-29 1990-06-26 Mentor Graphics Corporation Method and apparatus for estimating fault coverage
JPH04148882A (ja) * 1990-10-12 1992-05-21 Hitachi Ltd 論理集積回路の故障位置指摘方法
US5717928A (en) * 1990-11-07 1998-02-10 Matra Hachette Sa System and a method for obtaining a mask programmable device using a logic description and a field programmable device implementing the logic description
US5483544A (en) * 1991-02-05 1996-01-09 Vlsi Technology, Inc. Vector-specific testability circuitry
WO1993016433A1 (en) * 1992-02-07 1993-08-19 Seiko Epson Corporation Hardware emulation accelerator and method
US5475624A (en) * 1992-04-30 1995-12-12 Schlumberger Technologies, Inc. Test generation by environment emulation
JPH06194415A (ja) * 1992-09-30 1994-07-15 American Teleph & Telegr Co <Att> 論理回路の試験方法とその装置
JP3212423B2 (ja) * 1993-09-30 2001-09-25 富士通株式会社 テストパターン作成装置
US5515384A (en) * 1994-03-01 1996-05-07 International Business Machines Corporation Method and system of fault diagnosis of application specific electronic circuits
US5570376A (en) * 1994-10-05 1996-10-29 Sun Microsystems, Inc. Method and apparatus for identifying faults within a system
US5724504A (en) * 1995-06-01 1998-03-03 International Business Machines Corporation Method for measuring architectural test coverage for design verification and building conformal test
US5712857A (en) * 1995-09-29 1998-01-27 Intel Corporation Methods and apparatus for correlating stuck-at fault test coverage and current leakage fault test coverage
KR100212608B1 (ko) * 1996-01-12 1999-08-02 가네꼬 히사시 Cmos 집적 회로 고장 진단 장치 및 진단 방법
US5923567A (en) * 1996-04-10 1999-07-13 Altera Corporation Method and device for test vector analysis
JP3018996B2 (ja) * 1996-07-29 2000-03-13 日本電気株式会社 故障個所特定化方法
US6058253A (en) * 1996-12-05 2000-05-02 Advanced Micro Devices, Inc. Method and apparatus for intrusive testing of a microprocessor feature
JP2982741B2 (ja) * 1997-05-13 1999-11-29 日本電気株式会社 集積回路の故障診断装置及びその記録媒体
US6182258B1 (en) * 1997-06-03 2001-01-30 Verisity Ltd. Method and apparatus for test generation during circuit design
US6141630A (en) 1997-08-07 2000-10-31 Verisity Design, Inc. System and method for automated design verification
US6292765B1 (en) * 1997-10-20 2001-09-18 O-In Design Automation Method for automatically searching for functional defects in a description of a circuit
JPH11149491A (ja) * 1997-11-17 1999-06-02 Toshiba Corp 故障検出率評価方法
US6223313B1 (en) * 1997-12-05 2001-04-24 Lightspeed Semiconductor Corporation Method and apparatus for controlling and observing data in a logic block-based asic
US6076173A (en) * 1997-12-31 2000-06-13 Intel Corporation Architectural coverage measure
US6237117B1 (en) * 1998-09-30 2001-05-22 Sun Microsystems, Inc. Method for testing circuit design using exhaustive test vector sequence
US6532440B1 (en) * 1998-10-16 2003-03-11 Fujitsu Limited Multiple error and fault diagnosis based on Xlists
US6253344B1 (en) * 1998-10-29 2001-06-26 Hewlett Packard Company System and method for testing a microprocessor with an onboard test vector generator
US6467058B1 (en) * 1999-01-20 2002-10-15 Nec Usa, Inc. Segmented compaction with pruning and critical fault elimination
JP3942765B2 (ja) * 1999-03-15 2007-07-11 株式会社アドバンテスト 半導体デバイスシミュレート装置及びそれを用いた半導体試験用プログラムデバッグ装置
US6631344B1 (en) * 1999-03-26 2003-10-07 Synopsys, Inc. Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation
US7281185B2 (en) * 1999-06-08 2007-10-09 Cadence Design (Israel) Ii Ltd. Method and apparatus for maximizing and managing test coverage
US6675138B1 (en) * 1999-06-08 2004-01-06 Verisity Ltd. System and method for measuring temporal coverage detection
US7114111B2 (en) * 1999-06-08 2006-09-26 Cadence Design (Isreal) Ii Ltd. Method and apparatus for maximizing test coverage
JP3842489B2 (ja) * 1999-06-30 2006-11-08 株式会社東芝 回路設計装置、回路設計方法および回路設計プログラムを格納したコンピュータ読み取り可能な記録媒体
JP2001021624A (ja) * 1999-07-07 2001-01-26 Fujitsu Ltd テストデータ生成システム及び方法並びにテストデータ生成プログラムを記録した記録媒体
US6968286B1 (en) * 1999-07-28 2005-11-22 Lsi Logic Corporation Functional-pattern management system for device verification
US6484135B1 (en) * 1999-08-30 2002-11-19 Hewlett-Packard Company Method for adaptive test generation via feedback from dynamic emulation
US6874135B2 (en) * 1999-09-24 2005-03-29 Nec Corporation Method for design validation using retiming
US6810372B1 (en) * 1999-12-07 2004-10-26 Hewlett-Packard Development Company, L.P. Multimodal optimization technique in test generation
US6615379B1 (en) * 1999-12-08 2003-09-02 Intel Corporation Method and apparatus for testing a logic device
JP4174167B2 (ja) * 2000-04-04 2008-10-29 株式会社アドバンテスト 半導体集積回路の故障解析方法および故障解析装置
US6342790B1 (en) * 2000-04-13 2002-01-29 Pmc-Sierra, Inc. High-speed, adaptive IDDQ measurement
US6865706B1 (en) * 2000-06-07 2005-03-08 Agilent Technologies, Inc. Apparatus and method for generating a set of test vectors using nonrandom filling
US6594610B1 (en) * 2001-02-21 2003-07-15 Xilinx, Inc. Fault emulation testing of programmable logic devices
US7337102B2 (en) * 2003-12-29 2008-02-26 The Mathworks, Inc. Hierarchical references or links in modeling environments
JP2002365346A (ja) * 2001-06-05 2002-12-18 Fujitsu Ltd テスト刺激コンパクション装置および方法
US6848088B1 (en) * 2002-06-17 2005-01-25 Mentor Graphics Corporation Measure of analysis performed in property checking
US6714035B2 (en) * 2002-06-28 2004-03-30 Hewlett-Packard Development Company, L.P. System and method for measuring fault coverage in an integrated circuit
US20040025123A1 (en) * 2002-08-01 2004-02-05 Angilivelil Josey G. System and method to facilitate evaluation of integrated circuits through delay testing
US6876934B2 (en) * 2002-08-14 2005-04-05 Atrenta Inc. Method for determining fault coverage from RTL description
US6948140B2 (en) * 2002-09-01 2005-09-20 Agilent Technologies, Inc. Methods and apparatus for characterizing board test coverage
US7210128B2 (en) * 2002-10-14 2007-04-24 Fujitsu Limited Event-driven observability enhanced coverage analysis
US7237166B2 (en) * 2002-10-23 2007-06-26 Hewlett-Packard Development Company, L.P. System and method for evaluating a multiprocessor system using a random bus traffic generation technique
JP3833984B2 (ja) * 2002-10-28 2006-10-18 株式会社東芝 テストベクタの生成装置、テストベクタの生成方法、半導体集積回路の故障解析装置、およびテストベクタを生成するためのプログラム
US7139955B2 (en) * 2002-12-17 2006-11-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Hierarchically-controlled automatic test pattern generation
JP4282334B2 (ja) * 2003-02-04 2009-06-17 株式会社アドバンテスト 試験装置
JP3974048B2 (ja) * 2003-02-06 2007-09-12 株式会社東芝 設計検証システム、設計検証方法及び設計検証プログラム
US7437640B2 (en) * 2003-02-13 2008-10-14 Janusz Rajski Fault diagnosis of compressed test responses having one or more unknown states
US6883150B2 (en) * 2003-03-14 2005-04-19 Hewlett-Packard Development Company, L.P. Automatic manufacturing test case generation method and system
US7181376B2 (en) * 2003-06-03 2007-02-20 International Business Machines Corporation Apparatus and method for coverage directed test
WO2005036402A1 (ja) * 2003-10-07 2005-04-21 Advantest Corporation テストプログラムデバッグ装置、半導体試験装置、テストプログラムデバッグ方法、及び試験方法
WO2005085888A1 (en) * 2004-03-05 2005-09-15 Vfs Technologies Limited Testing of embedded systems
US7239978B2 (en) * 2004-03-31 2007-07-03 Wu-Tung Cheng Compactor independent fault diagnosis
US7137083B2 (en) * 2004-04-01 2006-11-14 Verigy Ipco Verification of integrated circuit tests using test simulation and integrated circuit simulation with simulated failure
US7437641B1 (en) * 2004-04-01 2008-10-14 Pmc-Sierra, Inc. Systems and methods for signature circuits
US7509600B2 (en) * 2004-04-22 2009-03-24 Janusz Rajski Generating test patterns having enhanced coverage of untargeted defects
US7203882B2 (en) * 2004-08-31 2007-04-10 International Business Machines Corporation Clustering-based approach for coverage-directed test generation
US7219287B1 (en) * 2004-09-29 2007-05-15 Xilinx, Inc. Automated fault diagnosis in a programmable device
US7237161B2 (en) * 2005-03-30 2007-06-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Remote integrated circuit testing method and apparatus
JP5066684B2 (ja) * 2006-03-28 2012-11-07 国立大学法人九州工業大学 生成装置、生成方法、生成方法をコンピュータに実行させることが可能なプログラム、及び、このプログラムを記録した記録媒体
JP4597898B2 (ja) * 2006-03-31 2010-12-15 住友電工デバイス・イノベーション株式会社 試験システム
US7640476B2 (en) * 2006-09-22 2009-12-29 Sun Microsystems Inc. Method and system for automated path delay test vector generation from functional tests
US7617468B2 (en) * 2007-07-31 2009-11-10 Synopsys, Inc. Method for automatic maximization of coverage in constrained stimulus driven simulation
JP4585559B2 (ja) * 2007-08-30 2010-11-24 株式会社東芝 半導体集積回路の検証装置
US7904286B2 (en) * 2007-09-14 2011-03-08 International Business Machines Corporation Method and apparatus for scheduling test vectors in a multiple core integrated circuit
US7844929B2 (en) * 2008-05-08 2010-11-30 Lsi Corporation Optimizing test code generation for verification environment
US7984353B2 (en) * 2008-08-29 2011-07-19 Advantest Corporation Test apparatus, test vector generate unit, test method, program, and recording medium
JP2010203937A (ja) * 2009-03-04 2010-09-16 Sony Corp テスト装置、テスト方法、およびプログラム
US8209141B2 (en) * 2009-03-11 2012-06-26 International Business Machines Corporation System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count

Also Published As

Publication number Publication date
US20070016394A1 (en) 2007-01-18
WO2007005586A1 (en) 2007-01-11
US20080109194A1 (en) 2008-05-08
US8090565B2 (en) 2012-01-03
US7970594B2 (en) 2011-06-28
EP1899876A1 (de) 2008-03-19
DE602006017698D1 (de) 2010-12-02
EP1899876B1 (de) 2010-10-20

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