ATE486321T1 - Priorisierung von interrupts in einer speichersteuerung - Google Patents

Priorisierung von interrupts in einer speichersteuerung

Info

Publication number
ATE486321T1
ATE486321T1 AT08774332T AT08774332T ATE486321T1 AT E486321 T1 ATE486321 T1 AT E486321T1 AT 08774332 T AT08774332 T AT 08774332T AT 08774332 T AT08774332 T AT 08774332T AT E486321 T1 ATE486321 T1 AT E486321T1
Authority
AT
Austria
Prior art keywords
interrupts
host
storage controller
memory controller
many
Prior art date
Application number
AT08774332T
Other languages
English (en)
Inventor
Brian Clark
Juan Coronado
Beth Peterson
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/772,734 external-priority patent/US7617345B2/en
Priority claimed from US11/772,742 external-priority patent/US7613860B2/en
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE486321T1 publication Critical patent/ATE486321T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt
    • G06F2213/2404—Generation of an interrupt or a group of interrupts after a predetermined number of interrupts

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Exchange Systems With Centralized Control (AREA)
AT08774332T 2007-07-02 2008-06-26 Priorisierung von interrupts in einer speichersteuerung ATE486321T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/772,734 US7617345B2 (en) 2007-07-02 2007-07-02 Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts
US11/772,742 US7613860B2 (en) 2007-07-02 2007-07-02 Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts
PCT/EP2008/058148 WO2009003903A1 (en) 2007-07-02 2008-06-26 Prioritization of interrupts in a storage controller

Publications (1)

Publication Number Publication Date
ATE486321T1 true ATE486321T1 (de) 2010-11-15

Family

ID=39767043

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08774332T ATE486321T1 (de) 2007-07-02 2008-06-26 Priorisierung von interrupts in einer speichersteuerung

Country Status (6)

Country Link
EP (1) EP2165264B1 (de)
KR (1) KR101154800B1 (de)
AT (1) ATE486321T1 (de)
BR (1) BRPI0811669B1 (de)
DE (1) DE602008003233D1 (de)
WO (1) WO2009003903A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5076967B2 (ja) * 2008-02-27 2012-11-21 富士通株式会社 情報処理システム、情報処理システムの制御方法、および情報処理システムの制御プログラム
US8023522B2 (en) 2009-03-30 2011-09-20 Intel Corporation Enabling long-term communication idleness for energy efficiency
US8560750B2 (en) * 2011-05-25 2013-10-15 Lsi Corporation Systems and methods for advanced interrupt scheduling and priority processing in a storage system environment
US9535777B2 (en) * 2013-11-22 2017-01-03 Intel Corporation Defect management policies for NAND flash memory
IL239113A (en) 2015-06-01 2016-12-29 Elbit Systems Land & C4I Ltd A system and method for determining audio characteristics from a body

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5542076A (en) * 1991-06-14 1996-07-30 Digital Equipment Corporation Method and apparatus for adaptive interrupt servicing in data processing system
US6615305B1 (en) * 1998-08-27 2003-09-02 Intel Corporation Interrupt pacing in data transfer unit
DE10160298A1 (de) * 2001-12-07 2003-06-18 Bosch Gmbh Robert Verfahren und Vorrichtung zur Verarbeitung von Interrput-Signalen
US7065598B2 (en) * 2002-12-20 2006-06-20 Intel Corporation Method, system, and article of manufacture for adjusting interrupt levels

Also Published As

Publication number Publication date
EP2165264A1 (de) 2010-03-24
KR20100037099A (ko) 2010-04-08
KR101154800B1 (ko) 2012-07-03
EP2165264B1 (de) 2010-10-27
DE602008003233D1 (de) 2010-12-09
BRPI0811669A2 (pt) 2016-11-08
BRPI0811669B1 (pt) 2020-01-14
WO2009003903A1 (en) 2009-01-08

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties