ATE487985T1 - Dynamische zugriffsteuerung einer funktion zu einem verteilten betriebsmittel - Google Patents

Dynamische zugriffsteuerung einer funktion zu einem verteilten betriebsmittel

Info

Publication number
ATE487985T1
ATE487985T1 AT02078450T AT02078450T ATE487985T1 AT E487985 T1 ATE487985 T1 AT E487985T1 AT 02078450 T AT02078450 T AT 02078450T AT 02078450 T AT02078450 T AT 02078450T AT E487985 T1 ATE487985 T1 AT E487985T1
Authority
AT
Austria
Prior art keywords
function
access
latency
access control
distributed resource
Prior art date
Application number
AT02078450T
Other languages
English (en)
Inventor
Perthuis Hugues De
Eric Desmicht
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE487985T1 publication Critical patent/ATE487985T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
AT02078450T 2001-08-31 2002-08-21 Dynamische zugriffsteuerung einer funktion zu einem verteilten betriebsmittel ATE487985T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0111321A FR2829253A1 (fr) 2001-08-31 2001-08-31 Controle d'acces dynamique d'une fonction a ressource collective

Publications (1)

Publication Number Publication Date
ATE487985T1 true ATE487985T1 (de) 2010-11-15

Family

ID=8866868

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02078450T ATE487985T1 (de) 2001-08-31 2002-08-21 Dynamische zugriffsteuerung einer funktion zu einem verteilten betriebsmittel

Country Status (7)

Country Link
US (1) US6959371B2 (de)
EP (1) EP1293909B1 (de)
JP (1) JP2003131937A (de)
KR (1) KR20030019235A (de)
AT (1) ATE487985T1 (de)
DE (1) DE60238237D1 (de)
FR (1) FR2829253A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2488516A (en) * 2011-02-15 2012-09-05 Advanced Risc Mach Ltd Using priority dependent delays to ensure that the average delay between accesses to a memory remains below a threshold
CN106383694A (zh) * 2016-09-09 2017-02-08 合普新能源科技有限公司 一种虚拟定时器定时方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5679324A (en) * 1979-11-30 1981-06-29 Fujitsu Ltd Memory access system
JPS57153323A (en) * 1981-03-17 1982-09-21 Nec Corp Information process controller
US4812968A (en) * 1986-11-12 1989-03-14 International Business Machines Corp. Method for controlling processor access to input/output devices
JPS63245551A (ja) * 1987-03-31 1988-10-12 Toshiba Corp マルチプロセツサシステムのメモリアクセス方式
JPH01255042A (ja) * 1988-04-04 1989-10-11 Hitachi Ltd 優先制御回路
JPH01263762A (ja) * 1988-04-13 1989-10-20 Mitsubishi Electric Corp マルチプロセッサシステム
US5506989A (en) * 1990-01-31 1996-04-09 Ibm Corporation Arbitration system limiting high priority successive grants
US5163140A (en) * 1990-02-26 1992-11-10 Nexgen Microsystems Two-level branch prediction cache
JPH04251366A (ja) * 1990-12-27 1992-09-07 Oki Electric Ind Co Ltd バスアービタ
JPH07200386A (ja) * 1993-12-28 1995-08-04 Toshiba Corp 共有メモリのアクセス制御装置および画像形成装置
JPH08278943A (ja) * 1995-04-05 1996-10-22 Fanuc Ltd 共有バス制御方式
US6112019A (en) * 1995-06-12 2000-08-29 Georgia Tech Research Corp. Distributed instruction queue
JPH10293744A (ja) * 1997-04-18 1998-11-04 Nec Corp Ｐｃｉバス・システム
US5848025A (en) * 1997-06-30 1998-12-08 Motorola, Inc. Method and apparatus for controlling a memory device in a page mode
DE69700328T2 (de) * 1997-09-13 1999-11-04 Hewlett-Packard Co., Palo Alto Ausgleich von Latenzzeit in einem Speicher
JPH11345165A (ja) * 1997-12-05 1999-12-14 Texas Instr Inc <Ti> アクセス待ち時間を減少するため優先度とバースト制御を使用するトラフィック・コントローラ
EP0921468B1 (de) 1997-12-05 2018-01-31 Texas Instruments Incorporated Steuerung eines Speichers zur Verkürzung der Zugriff-Latenzzeit unter Verwendung von Speicherzustandsinformation
US6266741B1 (en) * 1998-06-15 2001-07-24 International Business Machines Corporation Method and apparatus to reduce system bus latency on a cache miss with address acknowledgments
US6438670B1 (en) * 1998-10-02 2002-08-20 International Business Machines Corporation Memory controller with programmable delay counter for tuning performance based on timing parameter of controlled memory storage device
US6282614B1 (en) * 1999-04-15 2001-08-28 National Semiconductor Corporation Apparatus and method for reducing the power consumption of a microprocessor with multiple levels of caches
US6324643B1 (en) * 1999-10-01 2001-11-27 Hitachi, Ltd. Branch prediction and target instruction control for processor

Also Published As

Publication number Publication date
KR20030019235A (ko) 2003-03-06
US20030046506A1 (en) 2003-03-06
JP2003131937A (ja) 2003-05-09
FR2829253A1 (fr) 2003-03-07
DE60238237D1 (de) 2010-12-23
US6959371B2 (en) 2005-10-25
EP1293909B1 (de) 2010-11-10
EP1293909A1 (de) 2003-03-19

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