ATE488842T1 - Integrierte schaltung mit speicherzellen mit einem programmierbaren widerstand und verfahren zum adressieren von speicherzellen mit einem programmierbaren widerstand - Google Patents
Integrierte schaltung mit speicherzellen mit einem programmierbaren widerstand und verfahren zum adressieren von speicherzellen mit einem programmierbaren widerstandInfo
- Publication number
- ATE488842T1 ATE488842T1 AT05790410T AT05790410T ATE488842T1 AT E488842 T1 ATE488842 T1 AT E488842T1 AT 05790410 T AT05790410 T AT 05790410T AT 05790410 T AT05790410 T AT 05790410T AT E488842 T1 ATE488842 T1 AT E488842T1
- Authority
- AT
- Austria
- Prior art keywords
- bus
- memory cells
- encoder
- programmable resistor
- check bits
- Prior art date
Links
- 230000005540 biological transmission Effects 0.000 abstract 2
- 238000001514 detection method Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0071—Write using write potential applied to access device gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
Landscapes
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP04104797 | 2004-09-30 | ||
| PCT/IB2005/052730 WO2006035326A1 (en) | 2004-09-30 | 2005-08-19 | Integrated circuit with memory cells comprising a programmable resistor and method for addressing memory cells comprising a programmable resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE488842T1 true ATE488842T1 (de) | 2010-12-15 |
Family
ID=35457343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT05790410T ATE488842T1 (de) | 2004-09-30 | 2005-08-19 | Integrierte schaltung mit speicherzellen mit einem programmierbaren widerstand und verfahren zum adressieren von speicherzellen mit einem programmierbaren widerstand |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8335103B2 (de) |
| EP (1) | EP1797566B1 (de) |
| JP (1) | JP2008515127A (de) |
| CN (1) | CN100568390C (de) |
| AT (1) | ATE488842T1 (de) |
| DE (1) | DE602005024840D1 (de) |
| WO (1) | WO2006035326A1 (de) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7679980B2 (en) * | 2006-11-21 | 2010-03-16 | Qimonda North America Corp. | Resistive memory including selective refresh operation |
| US20100182044A1 (en) * | 2007-03-13 | 2010-07-22 | Easic Corporation | Programming and circuit topologies for programmable vias |
| JP5334995B2 (ja) | 2008-01-16 | 2013-11-06 | エヌエックスピー ビー ヴィ | 相変化材料層を有する多層構造およびその製造方法 |
| US8294488B1 (en) * | 2009-04-24 | 2012-10-23 | Adesto Technologies Corporation | Programmable impedance element circuits and methods |
| KR20120098326A (ko) * | 2011-02-28 | 2012-09-05 | 에스케이하이닉스 주식회사 | 반도체 장치 및 데이터 처리방법 |
| CN103592883B (zh) * | 2013-12-02 | 2016-01-20 | 哈尔滨工业大学 | 基于dsp的多路精密可编程电阻模块及其控制方法 |
| US11646079B2 (en) * | 2020-08-26 | 2023-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory cell including programmable resistors with transistor components |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB8627488D0 (en) * | 1986-11-18 | 1986-12-17 | British Petroleum Co Plc | Memory matrix |
| US5761115A (en) | 1996-05-30 | 1998-06-02 | Axon Technologies Corporation | Programmable metallization cell structure and method of making same |
| US6314014B1 (en) * | 1999-12-16 | 2001-11-06 | Ovonyx, Inc. | Programmable resistance memory arrays with reference cells |
| JP4667594B2 (ja) | 2000-12-25 | 2011-04-13 | ルネサスエレクトロニクス株式会社 | 薄膜磁性体記憶装置 |
| DE60137788D1 (de) | 2001-12-27 | 2009-04-09 | St Microelectronics Srl | Architektur einer nichtflüchtigen Phasenwechsel -Speichermatrix |
| CN100337333C (zh) * | 2002-04-10 | 2007-09-12 | 松下电器产业株式会社 | 非易失性触发器 |
| JP4282314B2 (ja) * | 2002-06-25 | 2009-06-17 | シャープ株式会社 | 記憶装置 |
| EP1532684A1 (de) | 2002-08-20 | 2005-05-25 | Koninklijke Philips Electronics N.V. | Ferroelektrische einrichtung und verfahren zur herstellung einer solchen einrichtung |
| EP1537584B1 (de) | 2002-09-11 | 2017-10-25 | Ovonyx Memory Technology, LLC | Programmierung eines phasenwechselmaterialspeicher |
| JP2004185755A (ja) * | 2002-12-05 | 2004-07-02 | Sharp Corp | 不揮発性半導体記憶装置 |
| JP4124635B2 (ja) * | 2002-12-05 | 2008-07-23 | シャープ株式会社 | 半導体記憶装置及びメモリセルアレイの消去方法 |
| DE60335208D1 (de) | 2002-12-19 | 2011-01-13 | Nxp Bv | Elektrisches bauelement mit einer schicht aus phasenwechsel-material und verfahren zur seiner herstellung |
| KR100479810B1 (ko) | 2002-12-30 | 2005-03-31 | 주식회사 하이닉스반도체 | 불휘발성 메모리 장치 |
| JP2004288282A (ja) * | 2003-03-20 | 2004-10-14 | Fujitsu Ltd | 半導体装置 |
| JP4254293B2 (ja) | 2003-03-25 | 2009-04-15 | 株式会社日立製作所 | 記憶装置 |
| JP4113493B2 (ja) | 2003-06-12 | 2008-07-09 | シャープ株式会社 | 不揮発性半導体記憶装置及びその制御方法 |
| US7180767B2 (en) * | 2003-06-18 | 2007-02-20 | Macronix International Co., Ltd. | Multi-level memory device and methods for programming and reading the same |
| WO2004114315A1 (ja) * | 2003-06-25 | 2004-12-29 | Matsushita Electric Industrial Co., Ltd. | 不揮発性メモリを駆動する方法 |
| JP4356542B2 (ja) | 2003-08-27 | 2009-11-04 | 日本電気株式会社 | 半導体装置 |
| DE10353641B4 (de) | 2003-11-17 | 2016-12-01 | Robert Bosch Gmbh | Brennstoffeinspritzventil |
| JP2005183619A (ja) * | 2003-12-18 | 2005-07-07 | Canon Inc | 不揮発メモリ装置 |
| JP4646636B2 (ja) * | 2004-02-20 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2005
- 2005-08-19 AT AT05790410T patent/ATE488842T1/de not_active IP Right Cessation
- 2005-08-19 US US11/576,459 patent/US8335103B2/en not_active Expired - Fee Related
- 2005-08-19 CN CN200580040979.4A patent/CN100568390C/zh not_active Expired - Fee Related
- 2005-08-19 WO PCT/IB2005/052730 patent/WO2006035326A1/en not_active Ceased
- 2005-08-19 JP JP2007534117A patent/JP2008515127A/ja not_active Withdrawn
- 2005-08-19 EP EP05790410A patent/EP1797566B1/de not_active Expired - Lifetime
- 2005-08-19 DE DE602005024840T patent/DE602005024840D1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN100568390C (zh) | 2009-12-09 |
| US20100214827A1 (en) | 2010-08-26 |
| CN101069241A (zh) | 2007-11-07 |
| WO2006035326A1 (en) | 2006-04-06 |
| US8335103B2 (en) | 2012-12-18 |
| DE602005024840D1 (de) | 2010-12-30 |
| EP1797566B1 (de) | 2010-11-17 |
| JP2008515127A (ja) | 2008-05-08 |
| EP1797566A1 (de) | 2007-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB2438116A (en) | Memory buffers for merging local data from memory modules | |
| US9621303B2 (en) | Method and apparatus for valid encoding | |
| ATE428984T1 (de) | Verfahren und vorrichtung zum senden von daten von mehreren quellen über einen kommunikationsbus | |
| DE50212947D1 (de) | Verfahren zur Übertragung von Daten über einen Datenbus | |
| ATE441187T1 (de) | Daten-strobe-synchronisationsschaltung und verfahren für doppeldatenraten-mehrbit- schreiboperationen | |
| WO2009051991A3 (en) | Balanced data bus inversion | |
| DE69602013D1 (de) | Parallelverarbeitungsredundanzs-vorrichtung und -verfahren für schnellere zugriffszeit und kleinere matrizeoberfläche | |
| DE602005010652D1 (de) | Entwurf für Kanalausrichtung, Fehlerbehandlung und Taktrouting unter Verwendung von festverdrahteten Blöcken zur Datenübertragung innerhalb von programmierbaren integrierten Schaltungen | |
| EP2187566A4 (de) | Verfahren und vorrichtung zur realisierung einer datenfehlerberichterstattung | |
| ATE488842T1 (de) | Integrierte schaltung mit speicherzellen mit einem programmierbaren widerstand und verfahren zum adressieren von speicherzellen mit einem programmierbaren widerstand | |
| JP2012198983A (ja) | 集積回路デバイス用の検査方法および装置 | |
| TW200739600A (en) | Multi-port memory device with serial input/output interface and control method thereof | |
| WO2008019274A3 (en) | Method and apparatus for reducing power consumption in a content addressable memory | |
| ATE393431T1 (de) | Datenkommunikationsmodul zur bereitstellung von fehlertoleranz und vergrösserter stabilität | |
| WO2009035964A3 (en) | Electronic fuse system and methods | |
| KR840007341A (ko) | 데이타 송수신 시스템 | |
| TW200601343A (en) | Semiconductor memory device and method of testing semiconductor memory device | |
| ATE422766T1 (de) | Schnittstelle und verfahren zur übertragung von bits an einen zweidraht-bus, der ein lin- protokoll anwendet | |
| TW200627477A (en) | Memory device employing open bit line architecture for providing identical data topology on repaired memory cell block and method thereof | |
| TW200510987A (en) | Method and related apparatus for outputting clock through data path | |
| JP2002319284A (ja) | データ伝送方法および装置 | |
| EP1517217A3 (de) | Schnittstellenschaltung und Taktausgabeverfahren dazu | |
| TW200511027A (en) | Information processing apparatus, memory, information processing method, and program | |
| JP6109090B2 (ja) | シリアル通信装置 | |
| KR102111069B1 (ko) | 데이터 리드 개시 결정 장치 및 그 방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |