ATE488932T1 - Gepufferter eingangsschalter - Google Patents

Gepufferter eingangsschalter

Info

Publication number
ATE488932T1
ATE488932T1 AT06727633T AT06727633T ATE488932T1 AT E488932 T1 ATE488932 T1 AT E488932T1 AT 06727633 T AT06727633 T AT 06727633T AT 06727633 T AT06727633 T AT 06727633T AT E488932 T1 ATE488932 T1 AT E488932T1
Authority
AT
Austria
Prior art keywords
input
inputs
input switch
queue
buffered input
Prior art date
Application number
AT06727633T
Other languages
English (en)
Inventor
Theodorus Denteneer
Ronald Rietman
Pestana Santiago Gonzalez
Nick Boot
Ivo Adan
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE488932T1 publication Critical patent/ATE488932T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/621—Individual queue per connection or flow, e.g. per VC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3018—Input queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3045—Virtual queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection or protection within a single switching element
    • H04L49/505—Corrective measures
    • H04L49/508—Head of Line Blocking Avoidance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
AT06727633T 2005-02-28 2006-02-21 Gepufferter eingangsschalter ATE488932T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05101524 2005-02-28
PCT/IB2006/050559 WO2006090332A2 (en) 2005-02-28 2006-02-21 Input buffered switch

Publications (1)

Publication Number Publication Date
ATE488932T1 true ATE488932T1 (de) 2010-12-15

Family

ID=36927808

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06727633T ATE488932T1 (de) 2005-02-28 2006-02-21 Gepufferter eingangsschalter

Country Status (7)

Country Link
US (1) US7961721B2 (de)
EP (1) EP1856860B1 (de)
JP (1) JP2008532408A (de)
CN (1) CN101142792A (de)
AT (1) ATE488932T1 (de)
DE (1) DE602006018268D1 (de)
WO (1) WO2006090332A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8261025B2 (en) 2007-11-12 2012-09-04 International Business Machines Corporation Software pipelining on a network on chip
US8526422B2 (en) * 2007-11-27 2013-09-03 International Business Machines Corporation Network on chip with partitions
US8490110B2 (en) * 2008-02-15 2013-07-16 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US20100002581A1 (en) * 2008-04-04 2010-01-07 The Arizona Board Of Regents On Behalf Of The University Of Arizona Method for Inter-Router Dual-Function Energy- and Area-Efficient Links for Network-on-Chips
US8423715B2 (en) 2008-05-01 2013-04-16 International Business Machines Corporation Memory management among levels of cache in a memory hierarchy
US8494833B2 (en) 2008-05-09 2013-07-23 International Business Machines Corporation Emulating a computer run time environment
US8392664B2 (en) * 2008-05-09 2013-03-05 International Business Machines Corporation Network on chip
US20090282211A1 (en) * 2008-05-09 2009-11-12 International Business Machines Network On Chip With Partitions
US8438578B2 (en) * 2008-06-09 2013-05-07 International Business Machines Corporation Network on chip with an I/O accelerator
US8195884B2 (en) 2008-09-18 2012-06-05 International Business Machines Corporation Network on chip with caching restrictions for pages of computer memory
WO2011148583A1 (ja) * 2010-05-27 2011-12-01 パナソニック株式会社 バス制御装置およびバス制御装置に指示を出力する制御装置
JP2012175357A (ja) * 2011-02-21 2012-09-10 Mitsubishi Electric Corp 入力バッファ型スイッチおよび入力装置
CN103248578B (zh) * 2013-05-15 2016-08-03 中国人民解放军国防科学技术大学 一种面向胖树型拓扑结构的8×8光交换阵列
US9294419B2 (en) * 2013-06-26 2016-03-22 Intel Corporation Scalable multi-layer 2D-mesh routers
CN104506310B (zh) * 2015-01-09 2018-05-18 中国人民解放军信息工程大学 一种多核密码处理器的片上网络拓扑结构及路由算法
US10157160B2 (en) * 2015-06-04 2018-12-18 Intel Corporation Handling a partition reset in a multi-root system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6618379B1 (en) 1998-12-08 2003-09-09 Nec Corporation RRGS-round-robin greedy scheduling for input/output terabit switches
US6791992B1 (en) * 1999-10-07 2004-09-14 The Regents Of The University Of California Earliest-deadline-first queuing cell switching architecture and method
EP1198098B1 (de) * 2000-09-27 2006-05-24 International Business Machines Corporation Vermittlungseinrichtung und verfahren mit getrennten Ausgangspuffern

Also Published As

Publication number Publication date
CN101142792A (zh) 2008-03-12
WO2006090332A2 (en) 2006-08-31
JP2008532408A (ja) 2008-08-14
US7961721B2 (en) 2011-06-14
US20090213863A1 (en) 2009-08-27
EP1856860A2 (de) 2007-11-21
EP1856860B1 (de) 2010-11-17
WO2006090332A3 (en) 2007-03-22
DE602006018268D1 (de) 2010-12-30

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Legal Events

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