ATE491991T1 - Mehrknoten system, bei dem die globale adresse, die durch ein verarbeitungsuntersystem erzeugt wird, globale-zu-lokale übersetzungsinformationen miteinschliesst - Google Patents

Mehrknoten system, bei dem die globale adresse, die durch ein verarbeitungsuntersystem erzeugt wird, globale-zu-lokale übersetzungsinformationen miteinschliesst

Info

Publication number
ATE491991T1
ATE491991T1 AT04749678T AT04749678T ATE491991T1 AT E491991 T1 ATE491991 T1 AT E491991T1 AT 04749678 T AT04749678 T AT 04749678T AT 04749678 T AT04749678 T AT 04749678T AT E491991 T1 ATE491991 T1 AT E491991T1
Authority
AT
Austria
Prior art keywords
global address
global
active device
node
address generated
Prior art date
Application number
AT04749678T
Other languages
English (en)
Inventor
Robert Cypher
Anders Landin
Erik Hagersten
Original Assignee
Oracle America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oracle America Inc filed Critical Oracle America Inc
Application granted granted Critical
Publication of ATE491991T1 publication Critical patent/ATE491991T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Telephonic Communication Services (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Game Rules And Presentations Of Slot Machines (AREA)
AT04749678T 2003-04-04 2004-04-02 Mehrknoten system, bei dem die globale adresse, die durch ein verarbeitungsuntersystem erzeugt wird, globale-zu-lokale übersetzungsinformationen miteinschliesst ATE491991T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US46057903P 2003-04-04 2003-04-04
PCT/US2004/010237 WO2004091136A2 (en) 2003-04-04 2004-04-02 Multi-node system in which global address generated by processing subsystem includes global to local translation information

Publications (1)

Publication Number Publication Date
ATE491991T1 true ATE491991T1 (de) 2011-01-15

Family

ID=33159783

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04749678T ATE491991T1 (de) 2003-04-04 2004-04-02 Mehrknoten system, bei dem die globale adresse, die durch ein verarbeitungsuntersystem erzeugt wird, globale-zu-lokale übersetzungsinformationen miteinschliesst

Country Status (5)

Country Link
US (1) US7360056B2 (de)
EP (1) EP1611513B1 (de)
AT (1) ATE491991T1 (de)
DE (1) DE602004030548D1 (de)
WO (1) WO2004091136A2 (de)

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US7685319B2 (en) 2004-09-28 2010-03-23 Cray Canada Corporation Low latency communication via memory windows
US8249089B2 (en) * 2006-09-29 2012-08-21 Intel Corporation Methods for pushing address translations mappings to PCI express endpoints
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US9069672B2 (en) * 2009-06-12 2015-06-30 Intel Corporation Extended fast memory access in a multiprocessor computer system
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
US20150370721A1 (en) * 2013-01-31 2015-12-24 Hewlett-Packard Development Company, L.P. Mapping mechanism for large shared address spaces
US10324841B2 (en) 2013-07-27 2019-06-18 Netlist, Inc. Memory module with local synchronization
US9575881B2 (en) 2014-12-04 2017-02-21 Qualcomm Incorporated Systems and methods for providing improved latency in a non-uniform memory architecture
US9542333B2 (en) 2014-12-04 2017-01-10 Qualcomm Incorporated Systems and methods for providing improved latency in a non-uniform memory architecture
US9892058B2 (en) * 2015-12-16 2018-02-13 Advanced Micro Devices, Inc. Centrally managed unified shared virtual address space
EP4325370A3 (de) 2016-04-25 2024-04-24 Netlist, Inc. Verfahren und vorrichtung für gleichmässigen speicherzugriff in einem speichercluster
US11768769B2 (en) 2016-04-25 2023-09-26 Netlist, Inc. Uniform memory access in a system having a plurality of nodes
US10970118B2 (en) 2017-08-02 2021-04-06 Advanced Micro Devices, Inc. Shareable FPGA compute engine
US11422812B2 (en) 2019-06-25 2022-08-23 Advanced Micro Devices, Inc. Method and apparatus for efficient programmable instructions in computer systems
KR20230114577A (ko) 2022-01-25 2023-08-01 삼성전자주식회사 데이터 처리 장치 및 방법
US20240311316A1 (en) * 2023-03-14 2024-09-19 Samsung Electronics Co., Ltd. Systems, methods, and apparatus for remote memory access by nodes

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JP3098344B2 (ja) * 1992-12-18 2000-10-16 富士通株式会社 データ転送処理方法及びデータ転送処理装置
JP2974526B2 (ja) * 1992-12-18 1999-11-10 富士通株式会社 データ転送処理方法及びデータ転送処理装置
US6088768A (en) * 1993-12-28 2000-07-11 International Business Machines Corporation Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication
US5845331A (en) * 1994-09-28 1998-12-01 Massachusetts Institute Of Technology Memory system including guarded pointers
US5940870A (en) * 1996-05-21 1999-08-17 Industrial Technology Research Institute Address translation for shared-memory multiprocessor clustering
US5887138A (en) * 1996-07-01 1999-03-23 Sun Microsystems, Inc. Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
US5892970A (en) 1996-07-01 1999-04-06 Sun Microsystems, Inc. Multiprocessing system configured to perform efficient block copy operations
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US6209064B1 (en) * 1998-01-07 2001-03-27 Fujitsu Limited Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system
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US6604184B2 (en) * 1999-06-30 2003-08-05 Intel Corporation Virtual memory mapping using region-based page tables
US6738889B2 (en) 1999-07-12 2004-05-18 International Business Machines Corporation Apparatus and method for providing simultaneous local and global addressing with hardware address translation
US6574714B2 (en) * 2001-02-12 2003-06-03 International Business Machines Corporation Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache
US6658538B2 (en) * 2001-06-21 2003-12-02 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control

Also Published As

Publication number Publication date
US7360056B2 (en) 2008-04-15
DE602004030548D1 (de) 2011-01-27
WO2004091136A3 (en) 2005-01-20
US20040260905A1 (en) 2004-12-23
EP1611513A2 (de) 2006-01-04
WO2004091136A2 (en) 2004-10-21
EP1611513B1 (de) 2010-12-15

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