ATE493699T1 - Schutz vor leistungsanalyse-angriffen - Google Patents
Schutz vor leistungsanalyse-angriffenInfo
- Publication number
- ATE493699T1 ATE493699T1 AT05702748T AT05702748T ATE493699T1 AT E493699 T1 ATE493699 T1 AT E493699T1 AT 05702748 T AT05702748 T AT 05702748T AT 05702748 T AT05702748 T AT 05702748T AT E493699 T1 ATE493699 T1 AT E493699T1
- Authority
- AT
- Austria
- Prior art keywords
- input data
- output data
- logical
- combinatorial
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
- G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
- G06F2207/7223—Randomisation as countermeasure against side channel attacks
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
- G06F2207/7266—Hardware adaptation, e.g. dual rail logic; calculate add and double simultaneously
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Logic Circuits (AREA)
- Storage Device Security (AREA)
- Fats And Perfumes (AREA)
- Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP04100279 | 2004-01-27 | ||
| PCT/IB2005/050254 WO2005073825A2 (en) | 2004-01-27 | 2005-01-21 | Protection against power analysis attacks |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE493699T1 true ATE493699T1 (de) | 2011-01-15 |
Family
ID=34814353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT05702748T ATE493699T1 (de) | 2004-01-27 | 2005-01-21 | Schutz vor leistungsanalyse-angriffen |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7907722B2 (de) |
| EP (1) | EP1711887B1 (de) |
| JP (1) | JP2007520951A (de) |
| KR (1) | KR20060127921A (de) |
| CN (1) | CN100565445C (de) |
| AT (1) | ATE493699T1 (de) |
| DE (1) | DE602005025593D1 (de) |
| WO (1) | WO2005073825A2 (de) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4783104B2 (ja) * | 2005-09-29 | 2011-09-28 | 株式会社東芝 | 暗号化/復号装置 |
| JP4960044B2 (ja) * | 2006-09-01 | 2012-06-27 | 株式会社東芝 | 暗号処理回路及びicカード |
| JP5203594B2 (ja) * | 2006-11-07 | 2013-06-05 | 株式会社東芝 | 暗号処理回路及び暗号処理方法 |
| US7853805B1 (en) * | 2007-02-02 | 2010-12-14 | Hrl Laboratories, Llc | Anti-tamper system |
| DE102007012726A1 (de) | 2007-03-16 | 2008-09-18 | Micronas Gmbh | Verschlüsselungsvorrichtung mit einem mehrstufigen Verschlüsselungsblock |
| FR2919739B1 (fr) * | 2007-08-03 | 2009-12-04 | Oberthur Card Syst Sa | Procede de traitement de donnees protege contre les attaques par generation de fautes et dispositif associe |
| US8091139B2 (en) * | 2007-11-01 | 2012-01-03 | Discretix Technologies Ltd. | System and method for masking arbitrary Boolean functions |
| JP5214317B2 (ja) * | 2008-04-25 | 2013-06-19 | 株式会社エヌ・ティ・ティ・データ | 暗号処理装置、暗号処理方法及びコンピュータプログラム |
| TWI527385B (zh) * | 2009-03-02 | 2016-03-21 | 美國亞德諾半導體公司 | 信號映射技術 |
| US8525545B1 (en) | 2011-08-26 | 2013-09-03 | Lockheed Martin Corporation | Power isolation during sensitive operations |
| US8624624B1 (en) | 2011-08-26 | 2014-01-07 | Lockheed Martin Corporation | Power isolation during sensitive operations |
| CN104769582B (zh) | 2012-11-02 | 2018-11-02 | 埃森哲环球服务有限公司 | 针对电网的实时数据管理 |
| CN104700044B (zh) * | 2015-03-03 | 2017-10-24 | 清华大学 | 寄存器输入输出互换的抗故障注入攻击方法和装置 |
| US10063569B2 (en) * | 2015-03-24 | 2018-08-28 | Intel Corporation | Custom protection against side channel attacks |
| US10210350B2 (en) | 2015-08-10 | 2019-02-19 | Samsung Electronics Co., Ltd. | Electronic device against side channel attacks |
| US11188682B2 (en) * | 2016-06-17 | 2021-11-30 | Arm Limited | Apparatus and method for masking power consumption of a processor |
| EP3264311B1 (de) | 2016-06-28 | 2021-01-13 | Eshard | Schutzverfahren und vorrichtung gegen eine seitenkanalanalyse |
| CN107547194A (zh) | 2016-06-28 | 2018-01-05 | 埃沙尔公司 | 免受侧信道分析的保护方法和设备 |
| WO2018002934A1 (en) * | 2016-06-29 | 2018-01-04 | Bar-Ilan University | Pseudo- asynchronous digital circuit design |
| US10521530B2 (en) | 2016-07-28 | 2019-12-31 | Bar-Ilan University | Data-dependent delay circuits |
| US11321460B2 (en) | 2018-02-28 | 2022-05-03 | Bar-Ilan University | Information redistribution to reduce side channel leakage |
| DE102018107114A1 (de) * | 2018-03-26 | 2019-09-26 | Infineon Technologies Ag | Seitenkanalgehärtete Operation |
| US11205018B2 (en) | 2019-02-14 | 2021-12-21 | International Business Machines Corporation | Device identification via chip manufacturing related fingerprints |
| JP7320962B2 (ja) * | 2019-03-18 | 2023-08-04 | 株式会社日立製作所 | データ管理システムおよびデータ管理方法 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0137995B1 (de) | 1983-10-14 | 1990-10-17 | Kabushiki Kaisha Toshiba | Einchip Mikrocomputer mit verschlüsselbarer Funktion des Programmspeichers |
| JP3088337B2 (ja) * | 1997-05-30 | 2000-09-18 | 三菱電機株式会社 | 暗号処理装置、icカード及び暗号処理方法 |
| AU6238499A (en) * | 1998-06-03 | 2000-01-10 | Cryptography Research, Inc. | Balanced cryptographic computational method and apparatus for leak minimization in smartcards and other cryptosystems |
| US6594760B1 (en) * | 1998-12-21 | 2003-07-15 | Pitney Bowes Inc. | System and method for suppressing conducted emissions by a cryptographic device |
| US7599491B2 (en) * | 1999-01-11 | 2009-10-06 | Certicom Corp. | Method for strengthening the implementation of ECDSA against power analysis |
| US6419159B1 (en) * | 1999-06-14 | 2002-07-16 | Microsoft Corporation | Integrated circuit device with power analysis protection circuitry |
| US6766455B1 (en) * | 1999-12-09 | 2004-07-20 | Pitney Bowes Inc. | System and method for preventing differential power analysis attacks (DPA) on a cryptographic device |
| FR2804524B1 (fr) * | 2000-01-31 | 2002-04-19 | Oberthur Card Systems Sas | Procede d'execution d'un protocole cryptographique entre deux entites electroniques |
| FR2818847A1 (fr) * | 2000-12-26 | 2002-06-28 | St Microelectronics Sa | Circuit logique a polarite variable |
| JP3904432B2 (ja) | 2001-11-16 | 2007-04-11 | 株式会社ルネサステクノロジ | 情報処理装置 |
| US7840803B2 (en) * | 2002-04-16 | 2010-11-23 | Massachusetts Institute Of Technology | Authentication of integrated circuits |
| DE10227618B4 (de) * | 2002-06-20 | 2007-02-01 | Infineon Technologies Ag | Logikschaltung |
| DE10244738B3 (de) * | 2002-09-25 | 2004-03-04 | Infineon Technologies Ag | Vorrichtung und Verfahren zum Umsetzen und Addierer |
| EP1496641A3 (de) * | 2003-07-07 | 2005-03-02 | Sony Corporation | Einrichtung, Verfahren und Computerprogramm zur kryptographischen Verarbeitung |
| DE10344647B3 (de) * | 2003-09-25 | 2005-02-17 | Infineon Technologies Ag | Schaltungsanordnung und Verfahren zur Verarbeitung eines Dual-Rail-Signals |
| FR2861474B1 (fr) * | 2003-10-24 | 2007-04-27 | Atmel Corp | Procede et appareil pour une periode de traitement variable dans un circuit integre |
| KR100585119B1 (ko) * | 2004-01-07 | 2006-06-01 | 삼성전자주식회사 | 암호화 장치, 암호화 방법 및 그 기록매체 |
-
2005
- 2005-01-21 WO PCT/IB2005/050254 patent/WO2005073825A2/en not_active Ceased
- 2005-01-21 KR KR1020067015064A patent/KR20060127921A/ko not_active Withdrawn
- 2005-01-21 US US10/587,727 patent/US7907722B2/en not_active Expired - Fee Related
- 2005-01-21 CN CNB200580003243XA patent/CN100565445C/zh not_active Expired - Fee Related
- 2005-01-21 JP JP2006550434A patent/JP2007520951A/ja not_active Withdrawn
- 2005-01-21 DE DE602005025593T patent/DE602005025593D1/de not_active Expired - Lifetime
- 2005-01-21 EP EP05702748A patent/EP1711887B1/de not_active Expired - Lifetime
- 2005-01-21 AT AT05702748T patent/ATE493699T1/de not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US7907722B2 (en) | 2011-03-15 |
| KR20060127921A (ko) | 2006-12-13 |
| WO2005073825A2 (en) | 2005-08-11 |
| EP1711887A2 (de) | 2006-10-18 |
| DE602005025593D1 (de) | 2011-02-10 |
| EP1711887B1 (de) | 2010-12-29 |
| WO2005073825A3 (en) | 2006-04-06 |
| JP2007520951A (ja) | 2007-07-26 |
| CN100565445C (zh) | 2009-12-02 |
| CN1914588A (zh) | 2007-02-14 |
| US20070160196A1 (en) | 2007-07-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |