ATE495551T1 - Herstellungsverfahren von einem soi-transistor mit selbstjustierter grundplatte und gate und mit einer vergrabenen oxidschicht mit veränderlicher dicke - Google Patents

Herstellungsverfahren von einem soi-transistor mit selbstjustierter grundplatte und gate und mit einer vergrabenen oxidschicht mit veränderlicher dicke

Info

Publication number
ATE495551T1
ATE495551T1 AT09162258T AT09162258T ATE495551T1 AT E495551 T1 ATE495551 T1 AT E495551T1 AT 09162258 T AT09162258 T AT 09162258T AT 09162258 T AT09162258 T AT 09162258T AT E495551 T1 ATE495551 T1 AT E495551T1
Authority
AT
Austria
Prior art keywords
layer
aliginated
gate
self
production
Prior art date
Application number
AT09162258T
Other languages
English (en)
Inventor
Claire Fenouillet-Beranger
Philippe Coronel
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE495551T1 publication Critical patent/ATE495551T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates

Landscapes

  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
AT09162258T 2008-06-11 2009-06-09 Herstellungsverfahren von einem soi-transistor mit selbstjustierter grundplatte und gate und mit einer vergrabenen oxidschicht mit veränderlicher dicke ATE495551T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0853868A FR2932609B1 (fr) 2008-06-11 2008-06-11 Transistor soi avec plan de masse et grille auto-alignes et oxyde enterre d'epaisseur variable

Publications (1)

Publication Number Publication Date
ATE495551T1 true ATE495551T1 (de) 2011-01-15

Family

ID=40328960

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09162258T ATE495551T1 (de) 2008-06-11 2009-06-09 Herstellungsverfahren von einem soi-transistor mit selbstjustierter grundplatte und gate und mit einer vergrabenen oxidschicht mit veränderlicher dicke

Country Status (5)

Country Link
US (1) US7910419B2 (de)
EP (1) EP2133919B1 (de)
AT (1) ATE495551T1 (de)
DE (1) DE602009000556D1 (de)
FR (1) FR2932609B1 (de)

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US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
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US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
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US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
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US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
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JP3462301B2 (ja) * 1995-06-16 2003-11-05 三菱電機株式会社 半導体装置及びその製造方法
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JP4525928B2 (ja) * 2005-12-27 2010-08-18 セイコーエプソン株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
FR2932609B1 (fr) 2010-12-24
DE602009000556D1 (de) 2011-02-24
EP2133919B1 (de) 2011-01-12
US20090311834A1 (en) 2009-12-17
US7910419B2 (en) 2011-03-22
EP2133919A1 (de) 2009-12-16
FR2932609A1 (fr) 2009-12-18

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