ATE496469T1 - Ausrichtung und entzerrung für mehrfache spuren einer seriellen verbindung - Google Patents

Ausrichtung und entzerrung für mehrfache spuren einer seriellen verbindung

Info

Publication number
ATE496469T1
ATE496469T1 AT06821287T AT06821287T ATE496469T1 AT E496469 T1 ATE496469 T1 AT E496469T1 AT 06821287 T AT06821287 T AT 06821287T AT 06821287 T AT06821287 T AT 06821287T AT E496469 T1 ATE496469 T1 AT E496469T1
Authority
AT
Austria
Prior art keywords
lanes
skew
equalization
alignment
serial connection
Prior art date
Application number
AT06821287T
Other languages
English (en)
Inventor
Tim Pontius
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE496469T1 publication Critical patent/ATE496469T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
AT06821287T 2005-11-04 2006-11-02 Ausrichtung und entzerrung für mehrfache spuren einer seriellen verbindung ATE496469T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US26482105A 2005-11-04 2005-11-04
PCT/IB2006/054056 WO2007052229A2 (en) 2005-11-04 2006-11-02 Alignment and deskew for multiple lanes of serial interconnect

Publications (1)

Publication Number Publication Date
ATE496469T1 true ATE496469T1 (de) 2011-02-15

Family

ID=38006276

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06821287T ATE496469T1 (de) 2005-11-04 2006-11-02 Ausrichtung und entzerrung für mehrfache spuren einer seriellen verbindung

Country Status (7)

Country Link
US (1) US8259755B2 (de)
EP (1) EP1958404B1 (de)
JP (1) JP2009525625A (de)
CN (1) CN101496367B (de)
AT (1) ATE496469T1 (de)
DE (1) DE602006019776D1 (de)
WO (1) WO2007052229A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2630445C (en) 2005-11-28 2016-11-15 Dsm Ip Assets B.V. Enzyme preparations yielding a clean taste
US9014563B2 (en) * 2006-12-11 2015-04-21 Cisco Technology, Inc. System and method for providing an Ethernet interface
US8199782B2 (en) 2009-02-20 2012-06-12 Altera Canada Co. Method of multiple lane distribution (MLD) deskew
CN101902271B (zh) * 2009-05-31 2013-03-06 国际商业机器公司 扭斜检测方法和设备及高速光通信接口
US8452908B2 (en) * 2009-12-29 2013-05-28 Juniper Networks, Inc. Low latency serial memory interface
JP5535672B2 (ja) 2010-02-02 2014-07-02 エヌイーシーコンピュータテクノ株式会社 シリアル転送装置及び方法
CN102394823B (zh) * 2011-11-03 2017-10-27 中兴通讯股份有限公司 一种多通道对齐去偏移的方法及装置
US9372501B2 (en) 2011-12-22 2016-06-21 Intel Corporation Block aligner-based dead cycle deskew method and apparatus
US9430604B2 (en) 2013-12-18 2016-08-30 Nxp B.V. Integrated circuit package and method
US9395744B2 (en) 2014-01-24 2016-07-19 International Business Machines Corporation De-skewing transmitted data
US20150213850A1 (en) * 2014-01-24 2015-07-30 Qualcomm Incorporated Serial data transmission for dynamic random access memory (dram) interfaces
CN105718412B (zh) * 2016-01-14 2018-10-26 深圳市紫光同创电子有限公司 一种通道频差补偿方法、通道控制方法、装置及系统
CN105718413B (zh) * 2016-01-14 2018-08-21 深圳市紫光同创电子有限公司 一种通道对齐方法、装置及系统
US10216653B2 (en) * 2016-10-03 2019-02-26 International Busiess Machines Corporation Pre-transmission data reordering for a serial interface
WO2018225534A1 (ja) * 2017-06-09 2018-12-13 ソニーセミコンダクタソリューションズ株式会社 受信装置、送信装置、制御方法、プログラム、および送受信システム
CN107591176A (zh) * 2017-08-25 2018-01-16 晶晨半导体(上海)股份有限公司 一种减弱芯片和存储器之间的辐射强度的方法
US10445265B2 (en) * 2017-10-20 2019-10-15 Cisco Technology, Inc. Method and apparatus for deskewing decentralized data streams
JP2020012934A (ja) * 2018-07-17 2020-01-23 株式会社Ｊｏｌｅｄ 表示パネルの駆動方法、駆動回路および表示装置
MY205100A (en) * 2020-12-29 2024-10-02 Skyechip Sdn Bhd A generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293626A (en) * 1990-06-08 1994-03-08 Cray Research, Inc. Clock distribution apparatus and processes particularly useful in multiprocessor systems
US6031847A (en) * 1997-07-01 2000-02-29 Silicon Graphics, Inc Method and system for deskewing parallel bus channels
US6167077A (en) 1997-12-23 2000-12-26 Lsi Logic Corporation Using multiple high speed serial lines to transmit high data rates while compensating for overall skew
US6512804B1 (en) 1999-04-07 2003-01-28 Applied Micro Circuits Corporation Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter
US7007099B1 (en) * 1999-05-03 2006-02-28 Lucent Technologies Inc. High speed multi-port serial-to-PCI bus interface
US7123660B2 (en) 2001-02-27 2006-10-17 Jazio, Inc. Method and system for deskewing parallel bus channels to increase data transfer rates
US6697974B2 (en) * 2001-03-14 2004-02-24 International Business Machines Corporation Method and apparatus for adaptively compensating skews during data transmission on a bus
US6839862B2 (en) 2001-05-31 2005-01-04 Koninklijke Philips Electronics N.V. Parallel data communication having skew intolerant data groups
JP4067787B2 (ja) 2001-07-05 2008-03-26 富士通株式会社 パラレル信号伝送装置
US7085950B2 (en) 2001-09-28 2006-08-01 Koninklijke Philips Electronics N.V. Parallel data communication realignment of data sent in multiple groups
US7187741B2 (en) 2001-10-31 2007-03-06 Nxp B.V. Clock domain crossing FIFO
JP4062078B2 (ja) * 2002-12-10 2008-03-19 株式会社日立製作所 スキュー調整装置
US20060209735A1 (en) 2003-08-11 2006-09-21 Evoy David R Auto realignment of multiple serial byte-lanes
US20070002939A1 (en) * 2005-06-29 2007-01-04 Tellabs Operations, Inc. Method and apparatus for testing a data path

Also Published As

Publication number Publication date
CN101496367B (zh) 2012-04-04
US20080279224A1 (en) 2008-11-13
EP1958404A2 (de) 2008-08-20
US8259755B2 (en) 2012-09-04
CN101496367A (zh) 2009-07-29
WO2007052229A3 (en) 2009-04-09
JP2009525625A (ja) 2009-07-09
WO2007052229A2 (en) 2007-05-10
DE602006019776D1 (de) 2011-03-03
EP1958404B1 (de) 2011-01-19

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