ATE498159T1 - Befehlsausgabe in gegenwart von ladefehlgriffen - Google Patents

Befehlsausgabe in gegenwart von ladefehlgriffen

Info

Publication number
ATE498159T1
ATE498159T1 AT02021394T AT02021394T ATE498159T1 AT E498159 T1 ATE498159 T1 AT E498159T1 AT 02021394 T AT02021394 T AT 02021394T AT 02021394 T AT02021394 T AT 02021394T AT E498159 T1 ATE498159 T1 AT E498159T1
Authority
AT
Austria
Prior art keywords
replay
queue
instructions
faults
processor
Prior art date
Application number
AT02021394T
Other languages
English (en)
Inventor
Tse-Yu Yeh
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE498159T1 publication Critical patent/ATE498159T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Power Steering Mechanism (AREA)
  • Control Of Eletrric Generators (AREA)
  • Steering Control In Accordance With Driving Conditions (AREA)
AT02021394T 2001-09-24 2002-09-24 Befehlsausgabe in gegenwart von ladefehlgriffen ATE498159T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US32434401P 2001-09-24 2001-09-24
US10/067,038 US7203817B2 (en) 2001-09-24 2002-02-04 Power consumption reduction in a pipeline by stalling instruction issue on a load miss

Publications (1)

Publication Number Publication Date
ATE498159T1 true ATE498159T1 (de) 2011-02-15

Family

ID=26747424

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02021394T ATE498159T1 (de) 2001-09-24 2002-09-24 Befehlsausgabe in gegenwart von ladefehlgriffen

Country Status (4)

Country Link
US (1) US7203817B2 (de)
EP (1) EP1296230B1 (de)
AT (1) ATE498159T1 (de)
DE (1) DE60239118D1 (de)

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US7502914B2 (en) * 2006-07-31 2009-03-10 Advanced Micro Devices, Inc. Transitive suppression of instruction replay
US7647518B2 (en) * 2006-10-10 2010-01-12 Apple Inc. Replay reduction for power saving
US7861066B2 (en) * 2007-07-20 2010-12-28 Advanced Micro Devices, Inc. Mechanism for predicting and suppressing instruction replay in a processor
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US10108427B2 (en) * 2014-12-14 2018-10-23 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
US10108421B2 (en) 2014-12-14 2018-10-23 Via Alliance Semiconductor Co., Ltd Mechanism to preclude shared ram-dependent load replays in an out-of-order processor
US10089112B2 (en) 2014-12-14 2018-10-02 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor
US10175984B2 (en) 2014-12-14 2019-01-08 Via Alliance Semiconductor Co., Ltd Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor
US10108430B2 (en) 2014-12-14 2018-10-23 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
WO2016097792A1 (en) * 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Apparatus and method to preclude load replays dependent on write combining memory space access in out-of-order processor
US10095514B2 (en) 2014-12-14 2018-10-09 Via Alliance Semiconductor Co., Ltd Mechanism to preclude I/O-dependent load replays in an out-of-order processor
US9703359B2 (en) * 2014-12-14 2017-07-11 Via Alliance Semiconductor Co., Ltd. Power saving mechanism to reduce load replays in out-of-order processor
WO2016097814A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Mechanism to preclude shared ram-dependent load replays in out-of-order processor
US10146539B2 (en) 2014-12-14 2018-12-04 Via Alliance Semiconductor Co., Ltd. Load replay precluding mechanism
US9645827B2 (en) 2014-12-14 2017-05-09 Via Alliance Semiconductor Co., Ltd. Mechanism to preclude load replays dependent on page walks in an out-of-order processor
US10146546B2 (en) 2014-12-14 2018-12-04 Via Alliance Semiconductor Co., Ltd Load replay precluding mechanism
US10114646B2 (en) 2014-12-14 2018-10-30 Via Alliance Semiconductor Co., Ltd Programmable load replay precluding mechanism
US10088881B2 (en) 2014-12-14 2018-10-02 Via Alliance Semiconductor Co., Ltd Mechanism to preclude I/O-dependent load replays in an out-of-order processor
US10120689B2 (en) 2014-12-14 2018-11-06 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor
US10083038B2 (en) 2014-12-14 2018-09-25 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on page walks in an out-of-order processor
US10108420B2 (en) 2014-12-14 2018-10-23 Via Alliance Semiconductor Co., Ltd Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor
US10146540B2 (en) 2014-12-14 2018-12-04 Via Alliance Semiconductor Co., Ltd Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor
WO2016097804A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Programmable load replay precluding mechanism
WO2016097790A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Apparatus and method to preclude non-core cache-dependent load replays in out-of-order processor
US9804845B2 (en) 2014-12-14 2017-10-31 Via Alliance Semiconductor Co., Ltd. Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor
US10127046B2 (en) 2014-12-14 2018-11-13 Via Alliance Semiconductor Co., Ltd. Mechanism to preclude uncacheable-dependent load replays in out-of-order processor
US9740271B2 (en) * 2014-12-14 2017-08-22 Via Alliance Semiconductor Co., Ltd. Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor
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EP3055768B1 (de) 2014-12-14 2018-10-31 VIA Alliance Semiconductor Co., Ltd. Mechanismus zum ausschliessen nicht speicherbarer lastwiedergaben in einem prozessor ausser betrieb
US10228944B2 (en) 2014-12-14 2019-03-12 Via Alliance Semiconductor Co., Ltd. Apparatus and method for programmable load replay preclusion
WO2016097802A1 (en) * 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Mechanism to preclude load replays dependent on long load cycles in an out-order processor
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US12314715B2 (en) * 2022-12-29 2025-05-27 SiFive, Inc. Tracking of store operations

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Also Published As

Publication number Publication date
DE60239118D1 (de) 2011-03-24
EP1296230A2 (de) 2003-03-26
US20030061470A1 (en) 2003-03-27
US7203817B2 (en) 2007-04-10
EP1296230B1 (de) 2011-02-09
EP1296230A3 (de) 2008-04-16

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties