ATE499651T1 - Datenübertragung durch ein rechnerdatenbus - Google Patents

Datenübertragung durch ein rechnerdatenbus

Info

Publication number
ATE499651T1
ATE499651T1 AT01997741T AT01997741T ATE499651T1 AT E499651 T1 ATE499651 T1 AT E499651T1 AT 01997741 T AT01997741 T AT 01997741T AT 01997741 T AT01997741 T AT 01997741T AT E499651 T1 ATE499651 T1 AT E499651T1
Authority
AT
Austria
Prior art keywords
bus
data
targets
target
transaction
Prior art date
Application number
AT01997741T
Other languages
English (en)
Inventor
Martin Whitaker
Original Assignee
Aspex Technology Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aspex Technology Ltd filed Critical Aspex Technology Ltd
Application granted granted Critical
Publication of ATE499651T1 publication Critical patent/ATE499651T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)
  • Circuits Of Receivers In General (AREA)
  • Traffic Control Systems (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
  • Communication Cables (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
AT01997741T 2000-11-21 2001-11-21 Datenübertragung durch ein rechnerdatenbus ATE499651T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0028353.1A GB0028353D0 (en) 2000-11-21 2000-11-21 Improvements relating to digital data communications
PCT/GB2001/005138 WO2002042917A2 (en) 2000-11-21 2001-11-21 Broadcasting data across a computer data bus

Publications (1)

Publication Number Publication Date
ATE499651T1 true ATE499651T1 (de) 2011-03-15

Family

ID=9903572

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01997741T ATE499651T1 (de) 2000-11-21 2001-11-21 Datenübertragung durch ein rechnerdatenbus

Country Status (8)

Country Link
US (1) US8046514B2 (de)
EP (1) EP1340155B1 (de)
JP (1) JP4231690B2 (de)
AT (1) ATE499651T1 (de)
AU (1) AU2002223856A1 (de)
DE (1) DE60144105D1 (de)
GB (1) GB0028353D0 (de)
WO (1) WO2002042917A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7765269B2 (en) * 2003-11-05 2010-07-27 Renesas Technology Corporation Communications system, and information processing device and control device incorporating said communications system
JP2005190067A (ja) * 2003-12-25 2005-07-14 Nec Corp 情報処理システム
KR100813256B1 (ko) * 2006-06-23 2008-03-13 삼성전자주식회사 버스 중재 장치 및 방법
US20080147939A1 (en) * 2006-12-15 2008-06-19 Riley Joseph D Broadcasting data on a peripheral component interconnect bus
JP5805546B2 (ja) 2012-01-13 2015-11-04 ルネサスエレクトロニクス株式会社 半導体装置

Family Cites Families (30)

* Cited by examiner, † Cited by third party
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US4692895A (en) * 1983-12-23 1987-09-08 American Telephone And Telegraph Company, At&T Bell Laboratories Microprocessor peripheral access control circuit
JPH03219345A (ja) * 1990-01-25 1991-09-26 Toshiba Corp 多ポートキャッシュメモリ制御装置
JPH0546476A (ja) * 1991-08-13 1993-02-26 Oki Electric Ind Co Ltd キヤツシユメモリ
US5507002A (en) * 1992-12-24 1996-04-09 At&T Global Information Solutions Company Peripheral component interconnect special cycle protocol using soft message IDS
JPH06259395A (ja) * 1993-03-02 1994-09-16 Toshiba Corp プロセススケジューリング方式
US5572703A (en) * 1994-03-01 1996-11-05 Intel Corporation Method and apparatus for snoop stretching using signals that convey snoop results
US5790831A (en) * 1994-11-01 1998-08-04 Opti Inc. VL-bus/PCI-bus bridge
MX9706592A (es) * 1995-03-17 1997-11-29 Intel Corp Protocolo de coherencia para multiprocesamiento cache en un conducto local.
US5634138A (en) * 1995-06-07 1997-05-27 Emulex Corporation Burst broadcasting on a peripheral component interconnect bus
US5940600A (en) * 1996-04-01 1999-08-17 Apple Computer, Inc. Isochronous channel having a linked list of buffers
US5953538A (en) * 1996-11-12 1999-09-14 Digital Equipment Corporation Method and apparatus providing DMA transfers between devices coupled to different host bus bridges
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US6058436A (en) * 1997-06-16 2000-05-02 Adaptec, Inc. Quick arbitration and select (QAS) protocol in SCSI interface for configuring a current target device to assert a QAS message code during a message-in phase
US6061794A (en) * 1997-09-30 2000-05-09 Compaq Computer Corp. System and method for performing secure device communications in a peer-to-peer bus architecture
US5983024A (en) * 1997-11-26 1999-11-09 Honeywell, Inc. Method and apparatus for robust data broadcast on a peripheral component interconnect bus
WO1999032976A1 (en) * 1997-12-18 1999-07-01 Koninklijke Philips Electronics N.V. Risc processor with concurrent snooping and instruction execution
EP0924623A3 (de) * 1997-12-22 2000-07-05 Compaq Computer Corporation Rechnersystem mit Arbitrierungsvorrichtung, die mehrere Bus-Master befähigt, auf einen Grafikbus zuzugreifen
US6397279B1 (en) * 1998-01-07 2002-05-28 Vlsi Technology, Inc. Smart retry system that reduces wasted bus transactions associated with master retries
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US6816934B2 (en) * 2000-12-22 2004-11-09 Hewlett-Packard Development Company, L.P. Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol
US6175889B1 (en) * 1998-10-21 2001-01-16 Compaq Computer Corporation Apparatus, method and system for a computer CPU and memory to high speed peripheral interconnect bridge having a plurality of physical buses with a single logical bus number
US6230225B1 (en) * 1998-12-01 2001-05-08 Compaq Computer Corp. Method and apparatus for multicasting on a bus
US6433785B1 (en) * 1999-04-09 2002-08-13 Intel Corporation Method and apparatus for improving processor to graphics device throughput
JP3791742B2 (ja) * 1999-05-28 2006-06-28 株式会社沖データ Ｐｃｉバス制御システム
US6336169B1 (en) * 1999-11-09 2002-01-01 International Business Machines Corporation Background kill system bus transaction to optimize coherency transactions on a multiprocessor system bus
US6694390B1 (en) * 2000-09-11 2004-02-17 Intel Corporation Managing bus transaction dependencies
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US7809873B2 (en) * 2008-04-11 2010-10-05 Sandisk Il Ltd. Direct data transfer between slave devices

Also Published As

Publication number Publication date
AU2002223856A1 (en) 2002-06-03
US20040220948A1 (en) 2004-11-04
JP2004526223A (ja) 2004-08-26
DE60144105D1 (de) 2011-04-07
US8046514B2 (en) 2011-10-25
EP1340155A2 (de) 2003-09-03
JP4231690B2 (ja) 2009-03-04
WO2002042917A3 (en) 2002-11-14
GB0028353D0 (en) 2001-01-03
EP1340155B1 (de) 2011-02-23
WO2002042917A2 (en) 2002-05-30

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