ATE500556T1 - Multiprozessorsystem, datenverarbeitungssystem, datenverarbeitungsverfahren und rechnerprogramm - Google Patents

Multiprozessorsystem, datenverarbeitungssystem, datenverarbeitungsverfahren und rechnerprogramm

Info

Publication number
ATE500556T1
ATE500556T1 AT01972530T AT01972530T ATE500556T1 AT E500556 T1 ATE500556 T1 AT E500556T1 AT 01972530 T AT01972530 T AT 01972530T AT 01972530 T AT01972530 T AT 01972530T AT E500556 T1 ATE500556 T1 AT E500556T1
Authority
AT
Austria
Prior art keywords
data processing
data
cell processors
computer program
cell
Prior art date
Application number
AT01972530T
Other languages
English (en)
Inventor
Nobuo Sasaki
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Application granted granted Critical
Publication of ATE500556T1 publication Critical patent/ATE500556T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Hardware Redundancy (AREA)
AT01972530T 2000-09-27 2001-09-27 Multiprozessorsystem, datenverarbeitungssystem, datenverarbeitungsverfahren und rechnerprogramm ATE500556T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000294732 2000-09-27
JP2001289588A JP3426223B2 (ja) 2000-09-27 2001-09-21 マルチプロセッサシステム、データ処理システム、データ処理方法、コンピュータプログラム
PCT/JP2001/008434 WO2002027513A1 (fr) 2000-09-27 2001-09-27 Systeme multiprocesseurs, systeme de traitement de donnees, procede de traitement de donnees et programme d'ordinateur

Publications (1)

Publication Number Publication Date
ATE500556T1 true ATE500556T1 (de) 2011-03-15

Family

ID=26600866

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01972530T ATE500556T1 (de) 2000-09-27 2001-09-27 Multiprozessorsystem, datenverarbeitungssystem, datenverarbeitungsverfahren und rechnerprogramm

Country Status (10)

Country Link
US (1) US7017158B2 (de)
EP (1) EP1324209B1 (de)
JP (1) JP3426223B2 (de)
KR (1) KR100866730B1 (de)
CN (1) CN1258154C (de)
AT (1) ATE500556T1 (de)
AU (1) AU2001292269A1 (de)
DE (1) DE60144155D1 (de)
TW (1) TWI229265B (de)
WO (1) WO2002027513A1 (de)

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US6989843B2 (en) * 2000-06-29 2006-01-24 Sun Microsystems, Inc. Graphics system with an improved filtering adder tree
US7346757B2 (en) 2002-10-08 2008-03-18 Rmi Corporation Advanced processor translation lookaside buffer management in a multithreaded system
US7334086B2 (en) * 2002-10-08 2008-02-19 Rmi Corporation Advanced processor with system on a chip interconnect technology
US9088474B2 (en) 2002-10-08 2015-07-21 Broadcom Corporation Advanced processor with interfacing messaging network to a CPU
US8478811B2 (en) 2002-10-08 2013-07-02 Netlogic Microsystems, Inc. Advanced processor with credit based scheme for optimal packet flow in a multi-processor system on a chip
US8037224B2 (en) 2002-10-08 2011-10-11 Netlogic Microsystems, Inc. Delegating network processor operations to star topology serial bus interfaces
US8176298B2 (en) 2002-10-08 2012-05-08 Netlogic Microsystems, Inc. Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline
US8015567B2 (en) * 2002-10-08 2011-09-06 Netlogic Microsystems, Inc. Advanced processor with mechanism for packet distribution at high line rate
US20050120185A1 (en) * 2003-12-01 2005-06-02 Sony Computer Entertainment Inc. Methods and apparatus for efficient multi-tasking
JP4794194B2 (ja) * 2005-04-01 2011-10-19 株式会社日立製作所 ストレージシステム及び記憶制御方法
JP4555145B2 (ja) * 2005-04-28 2010-09-29 富士通株式会社 バッチスケジューリングプログラム、バッチスケジューリング方法およびバッチスケジューリング装置
US7444525B2 (en) * 2005-05-25 2008-10-28 Sony Computer Entertainment Inc. Methods and apparatus for reducing leakage current in a disabled SOI circuit
US7970956B2 (en) * 2006-03-27 2011-06-28 Ati Technologies, Inc. Graphics-processing system and method of broadcasting write requests to multiple graphics devices
US9596324B2 (en) 2008-02-08 2017-03-14 Broadcom Corporation System and method for parsing and allocating a plurality of packets to processor core threads
JP5039950B2 (ja) 2008-03-21 2012-10-03 インターナショナル・ビジネス・マシーンズ・コーポレーション オブジェクト移動制御システム、オブジェクト移動制御方法、サーバ及びコンピュータプログラム
US8327114B1 (en) 2008-07-07 2012-12-04 Ovics Matrix processor proxy systems and methods
US8145880B1 (en) 2008-07-07 2012-03-27 Ovics Matrix processor data switch routing systems and methods
US7870365B1 (en) 2008-07-07 2011-01-11 Ovics Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel
US8131975B1 (en) 2008-07-07 2012-03-06 Ovics Matrix processor initialization systems and methods
US7958341B1 (en) 2008-07-07 2011-06-07 Ovics Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory
CN101478785B (zh) * 2009-01-21 2010-08-04 华为技术有限公司 资源池管理系统及信号处理方法
JP4539889B2 (ja) * 2009-02-18 2010-09-08 日本電気株式会社 プロセッサ及びデータ収集方法
KR101651871B1 (ko) * 2009-12-28 2016-09-09 삼성전자주식회사 멀티코어 시스템 상에서 단위 작업을 할당하는 방법 및 그 장치
US8850262B2 (en) * 2010-10-12 2014-09-30 International Business Machines Corporation Inter-processor failure detection and recovery
CN102306371B (zh) * 2011-07-14 2013-09-18 华中科技大学 一种分层并行的模块化序列图像实时处理装置
KR101863605B1 (ko) 2011-09-19 2018-07-06 삼성전자주식회사 스트림 데이터를 고속으로 처리하는 프로세서
US20130081028A1 (en) * 2011-09-23 2013-03-28 Royce A. Levien Receiving discrete interface device subtask result data and acquiring task result data
US9269063B2 (en) 2011-09-23 2016-02-23 Elwha Llc Acquiring and transmitting event related tasks and subtasks to interface devices
CN106936994B (zh) 2017-03-10 2019-10-01 Oppo广东移动通信有限公司 一种广播接收者的控制方法、装置及移动终端
JP7038608B2 (ja) * 2018-06-15 2022-03-18 ルネサスエレクトロニクス株式会社 半導体装置
WO2020084693A1 (ja) * 2018-10-23 2020-04-30 富士通株式会社 演算処理装置及び演算処理装置の制御方法
CN111290697B (zh) * 2018-12-07 2022-01-28 上海寒武纪信息科技有限公司 数据压缩方法、编码电路和运算装置
CN120010516B (zh) * 2025-02-14 2025-11-11 重庆邮电大学 一种森林火灾中面向移动节点的避障无人机数据收集方法

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JPS61283976A (ja) 1985-06-11 1986-12-13 Sanyo Electric Co Ltd パタ−ン認識装置
US4739476A (en) * 1985-08-01 1988-04-19 General Electric Company Local interconnection scheme for parallel processing architectures
JPH0247757A (ja) 1988-08-09 1990-02-16 Sanyo Electric Co Ltd 情報処理装置
JPH0814816B2 (ja) 1988-09-19 1996-02-14 富士通株式会社 並列計算機
DE68920388T2 (de) 1988-09-19 1995-05-11 Fujitsu Ltd Paralleles Rechnersystem mit Verwendung eines SIMD-Verfahrens.
JP2850387B2 (ja) 1989-07-31 1999-01-27 株式会社日立製作所 データ伝送方式
DE69033434T2 (de) 1989-07-31 2000-08-03 Hitachi, Ltd. Datenverarbeitungssystem und Datenübertragungs- und -verarbeitungsverfahren
JP2642039B2 (ja) * 1992-05-22 1997-08-20 インターナショナル・ビジネス・マシーンズ・コーポレイション アレイ・プロセッサ
US5511212A (en) * 1993-06-10 1996-04-23 Rockoff; Todd E. Multi-clock SIMD computer and instruction-cache-enhancement thereof
JPH0784966A (ja) 1993-08-06 1995-03-31 Toshiba Corp データ処理装置
US6516403B1 (en) * 1999-04-28 2003-02-04 Nec Corporation System for synchronizing use of critical sections by multiple processors using the corresponding flag bits in the communication registers and access control register

Also Published As

Publication number Publication date
EP1324209A4 (de) 2008-12-17
JP3426223B2 (ja) 2003-07-14
US20020059509A1 (en) 2002-05-16
DE60144155D1 (de) 2011-04-14
US7017158B2 (en) 2006-03-21
AU2001292269A1 (en) 2002-04-08
EP1324209B1 (de) 2011-03-02
CN1258154C (zh) 2006-05-31
WO2002027513A1 (fr) 2002-04-04
CN1392985A (zh) 2003-01-22
EP1324209A1 (de) 2003-07-02
JP2002175288A (ja) 2002-06-21
KR100866730B1 (ko) 2008-11-03
KR20020059430A (ko) 2002-07-12
TWI229265B (en) 2005-03-11

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