ATE502335T1 - Verfahren und vorrichtungen zur bereitstellung früher antworten aus einem abgesetzten daten- cache - Google Patents

Verfahren und vorrichtungen zur bereitstellung früher antworten aus einem abgesetzten daten- cache

Info

Publication number
ATE502335T1
ATE502335T1 AT04757398T AT04757398T ATE502335T1 AT E502335 T1 ATE502335 T1 AT E502335T1 AT 04757398 T AT04757398 T AT 04757398T AT 04757398 T AT04757398 T AT 04757398T AT E502335 T1 ATE502335 T1 AT E502335T1
Authority
AT
Austria
Prior art keywords
remote
data cache
distributed data
request
early response
Prior art date
Application number
AT04757398T
Other languages
English (en)
Inventor
David Glasco
Original Assignee
Newisys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Newisys Inc filed Critical Newisys Inc
Application granted granted Critical
Publication of ATE502335T1 publication Critical patent/ATE502335T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/082—Associative directories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Computer And Data Communications (AREA)
  • Information Transfer Between Computers (AREA)
AT04757398T 2003-08-05 2004-07-29 Verfahren und vorrichtungen zur bereitstellung früher antworten aus einem abgesetzten daten- cache ATE502335T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/635,703 US7249224B2 (en) 2003-08-05 2003-08-05 Methods and apparatus for providing early responses from a remote data cache
PCT/US2004/024685 WO2005017755A1 (en) 2003-08-05 2004-07-29 Methods and apparatus for providing early responses from a remote data cache

Publications (1)

Publication Number Publication Date
ATE502335T1 true ATE502335T1 (de) 2011-04-15

Family

ID=34116290

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04757398T ATE502335T1 (de) 2003-08-05 2004-07-29 Verfahren und vorrichtungen zur bereitstellung früher antworten aus einem abgesetzten daten- cache

Country Status (8)

Country Link
US (1) US7249224B2 (de)
EP (1) EP1652091B1 (de)
JP (1) JP2007501466A (de)
CN (1) CN1860452A (de)
AT (1) ATE502335T1 (de)
CA (1) CA2533203A1 (de)
DE (1) DE602004031852D1 (de)
WO (1) WO2005017755A1 (de)

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US10452593B1 (en) * 2018-05-03 2019-10-22 Arm Limited High-performance streaming of ordered write stashes to enable optimized data sharing between I/O masters and CPUs
US10936496B2 (en) * 2019-06-07 2021-03-02 Micron Technology, Inc. Managing collisions in a non-volatile memory system with a coherency checker
US10980756B1 (en) 2020-03-16 2021-04-20 First Wave Bio, Inc. Methods of treatment
US11354239B2 (en) * 2020-09-18 2022-06-07 Microsoft Technology Licensing, Llc Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices
US12417179B2 (en) 2023-12-28 2025-09-16 Advanced Micro Devices, Inc. Adaptive system probe action to minimize input/output dirty data transfers

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Also Published As

Publication number Publication date
JP2007501466A (ja) 2007-01-25
EP1652091B1 (de) 2011-03-16
EP1652091A4 (de) 2008-10-29
US20050033924A1 (en) 2005-02-10
WO2005017755A1 (en) 2005-02-24
US7249224B2 (en) 2007-07-24
CN1860452A (zh) 2006-11-08
DE602004031852D1 (de) 2011-04-28
EP1652091A1 (de) 2006-05-03
CA2533203A1 (en) 2005-02-24

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