ATE502398T1 - Spannungspufferungsgehäuse für ein halbleiterbauelement - Google Patents

Spannungspufferungsgehäuse für ein halbleiterbauelement

Info

Publication number
ATE502398T1
ATE502398T1 AT07700632T AT07700632T ATE502398T1 AT E502398 T1 ATE502398 T1 AT E502398T1 AT 07700632 T AT07700632 T AT 07700632T AT 07700632 T AT07700632 T AT 07700632T AT E502398 T1 ATE502398 T1 AT E502398T1
Authority
AT
Austria
Prior art keywords
semiconductor component
stress buffering
voltage buffering
buffering housing
housing
Prior art date
Application number
AT07700632T
Other languages
English (en)
Inventor
Hendrik Hochstenbach
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=37964096&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE502398(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE502398T1 publication Critical patent/ATE502398T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
  • Die Bonding (AREA)
AT07700632T 2006-01-24 2007-01-18 Spannungspufferungsgehäuse für ein halbleiterbauelement ATE502398T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06100793 2006-01-24
PCT/IB2007/050174 WO2007085988A1 (en) 2006-01-24 2007-01-18 Stress buffering package for a semiconductor component

Publications (1)

Publication Number Publication Date
ATE502398T1 true ATE502398T1 (de) 2011-04-15

Family

ID=37964096

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07700632T ATE502398T1 (de) 2006-01-24 2007-01-18 Spannungspufferungsgehäuse für ein halbleiterbauelement

Country Status (8)

Country Link
US (1) US8338967B2 (de)
EP (1) EP1979942B1 (de)
JP (1) JP2009524922A (de)
CN (1) CN101371357B (de)
AT (1) ATE502398T1 (de)
DE (1) DE602007013181D1 (de)
TW (1) TW200735302A (de)
WO (1) WO2007085988A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
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US20080308922A1 (en) * 2007-06-14 2008-12-18 Yiwen Zhang Method for packaging semiconductors at a wafer level
CN101765913B (zh) 2007-07-30 2012-10-03 Nxp股份有限公司 底部粗糙度减小的半导体部件的应力缓冲元件
US8039960B2 (en) * 2007-09-21 2011-10-18 Stats Chippac, Ltd. Solder bump with inner core pillar in semiconductor package
JP5062022B2 (ja) * 2008-05-08 2012-10-31 富士通株式会社 電子部品装置
US8035219B2 (en) * 2008-07-18 2011-10-11 Raytheon Company Packaging semiconductors at wafer level
JP2011165862A (ja) * 2010-02-09 2011-08-25 Sony Corp 半導体装置、チップ・オン・チップの実装構造、半導体装置の製造方法及びチップ・オン・チップの実装構造の形成方法
US8685793B2 (en) * 2010-09-16 2014-04-01 Tessera, Inc. Chip assembly having via interconnects joined by plating
US9137903B2 (en) * 2010-12-21 2015-09-15 Tessera, Inc. Semiconductor chip assembly and method for making same
US8643196B2 (en) * 2011-07-27 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for bump to landing trace ratio
US20130320451A1 (en) 2012-06-01 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") Semiconductor device having non-orthogonal element
US20130341780A1 (en) * 2012-06-20 2013-12-26 Infineon Technologies Ag Chip arrangements and a method for forming a chip arrangement
JP6225414B2 (ja) * 2012-11-16 2017-11-08 セイコーエプソン株式会社 半導体装置
US9397048B1 (en) * 2015-03-23 2016-07-19 Inotera Memories, Inc. Semiconductor structure and manufacturing method thereof
TWI562255B (en) * 2015-05-04 2016-12-11 Chipmos Technologies Inc Chip package structure and manufacturing method thereof
US10037957B2 (en) 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
US11029227B2 (en) 2018-06-04 2021-06-08 Vitesco Technologies USA, LLC CSOI MEMS pressure sensing element with stress equalizers
DE102019207963B4 (de) * 2018-06-04 2023-11-09 Vitesco Technologies USA, LLC (n.d.Ges.d.Staates Delaware) Csoi - mems-druckerfassungselement mit spannungsausgleichern
US11557499B2 (en) * 2020-10-16 2023-01-17 Applied Materials, Inc. Methods and apparatus for prevention of component cracking using stress relief layer

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JPS49112570A (de) * 1973-02-23 1974-10-26
JPS52150966A (en) * 1976-06-11 1977-12-15 Hitachi Ltd Semiconductor device
GB2097998B (en) 1981-05-06 1985-05-30 Standard Telephones Cables Ltd Mounting of integrated circuits
GB2135525B (en) 1983-02-22 1986-06-18 Smiths Industries Plc Heat-dissipating chip carrier substrates
JPH0513418A (ja) * 1991-07-04 1993-01-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3412969B2 (ja) * 1995-07-17 2003-06-03 株式会社東芝 半導体装置及びその製造方法
US5956088A (en) * 1995-11-21 1999-09-21 Imedia Corporation Method and apparatus for modifying encoded digital video for improved channel utilization
TW448524B (en) 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
JP4310647B2 (ja) * 1997-01-17 2009-08-12 セイコーエプソン株式会社 半導体装置及びその製造方法
JPH11266499A (ja) * 1998-03-18 1999-09-28 Hosiden Corp エレクトレットコンデンサマイクロホン
JP2000183104A (ja) * 1998-12-15 2000-06-30 Texas Instr Inc <Ti> 集積回路上でボンディングするためのシステム及び方法
JP2000278692A (ja) * 1999-03-25 2000-10-06 Victor Co Of Japan Ltd 圧縮データ処理方法及び処理装置並びに記録再生システム
JP3450238B2 (ja) * 1999-11-04 2003-09-22 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US6396156B1 (en) * 2000-09-07 2002-05-28 Siliconware Precision Industries Co., Ltd. Flip-chip bonding structure with stress-buffering property and method for making the same
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Also Published As

Publication number Publication date
EP1979942B1 (de) 2011-03-16
CN101371357A (zh) 2009-02-18
EP1979942A1 (de) 2008-10-15
WO2007085988A1 (en) 2007-08-02
CN101371357B (zh) 2011-04-13
TW200735302A (en) 2007-09-16
JP2009524922A (ja) 2009-07-02
DE602007013181D1 (de) 2011-04-28
US8338967B2 (en) 2012-12-25
US20100224987A1 (en) 2010-09-09

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