ATE505569T1 - Verfahren zur herstellung einer struktur mit wenigstens einer lagegenauen zone von einem oder mehreren halbleiter-nanokristallen - Google Patents
Verfahren zur herstellung einer struktur mit wenigstens einer lagegenauen zone von einem oder mehreren halbleiter-nanokristallenInfo
- Publication number
- ATE505569T1 ATE505569T1 AT05106613T AT05106613T ATE505569T1 AT E505569 T1 ATE505569 T1 AT E505569T1 AT 05106613 T AT05106613 T AT 05106613T AT 05106613 T AT05106613 T AT 05106613T AT E505569 T1 ATE505569 T1 AT E505569T1
- Authority
- AT
- Austria
- Prior art keywords
- zone
- producing
- semiconductor nanocrystals
- film
- positional zone
- Prior art date
Links
Classifications
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/402—Single electron transistors; Coulomb blockade transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/962—Quantum dots and lines
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Metallurgy (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0451589A FR2873491B1 (fr) | 2004-07-20 | 2004-07-20 | Procede de realisation d'une structure dotee d'au moins une zone d'un ou plusieurs nanocristaux semi-conducteurs localisee avec precision |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE505569T1 true ATE505569T1 (de) | 2011-04-15 |
Family
ID=34948371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT05106613T ATE505569T1 (de) | 2004-07-20 | 2005-07-19 | Verfahren zur herstellung einer struktur mit wenigstens einer lagegenauen zone von einem oder mehreren halbleiter-nanokristallen |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7713850B2 (de) |
| EP (1) | EP1619277B1 (de) |
| AT (1) | ATE505569T1 (de) |
| DE (1) | DE602005027425D1 (de) |
| FR (1) | FR2873491B1 (de) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2910456B1 (fr) * | 2006-12-21 | 2018-02-09 | Commissariat A L'energie Atomique | Procede de realisation de microfils et/ou de nanofils |
| FR2910455B1 (fr) * | 2006-12-21 | 2009-04-03 | Commissariat Energie Atomique | Procede de realisation de micro-cavites non alignees et a differentes profondeurs |
| FR2974941B1 (fr) | 2011-05-06 | 2013-06-14 | Commissariat Energie Atomique | Procede de realisation de nanocristaux de |
| FR2974940B1 (fr) | 2011-05-06 | 2015-11-13 | Commissariat Energie Atomique | Procede de realisation de nanocristaux de semi-conducteur orientes selon une direction pre-definie |
| DE102012017503A1 (de) * | 2012-05-30 | 2013-12-19 | Eads Deutschland Gmbh | Verfahren zur Nanostrukturierung von anorganischen und organischen Materialien durch kontinuierliche Bestrahlung mit einem Teilchenstrahl |
| FR3046155B1 (fr) * | 2015-12-28 | 2020-01-10 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de realisation de nanocristaux a dimensions et densite controlees |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2779414B2 (ja) * | 1988-12-01 | 1998-07-23 | セイコーインスツルメンツ株式会社 | ミクロ断面の加工・観察方法 |
| JP3156878B2 (ja) * | 1992-04-30 | 2001-04-16 | 株式会社東芝 | 半導体装置およびその製造方法 |
| DE19618447A1 (de) * | 1996-05-08 | 1997-11-20 | Studiengesellschaft Kohle Mbh | Lithographisches Verfahren zur Erzeugung von Nanostrukturen auf Oberflächen |
| JP2929005B1 (ja) * | 1998-07-01 | 1999-08-03 | 科学技術庁金属材料技術研究所長 | Si微結晶構造の製造方法 |
| US7084016B1 (en) * | 1998-07-17 | 2006-08-01 | Semiconductor Energy Laboratory Co., Ltd. | Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same |
| JP2001023899A (ja) * | 1999-07-13 | 2001-01-26 | Hitachi Ltd | 半導体薄膜とその半導体膜を用いた液晶表示装置及びその製造方法 |
| KR20020058151A (ko) * | 2000-12-29 | 2002-07-12 | 박호군 | 집속이온빔을 이용하는 상온동작 단전자 터널링트랜지스터 제조방법 |
| EP1229590A1 (de) * | 2001-01-31 | 2002-08-07 | Japan Science and Technology Corporation | Korrelative Ladungsverschiebungsanordnung und Verfahren zur Herstellung |
| JP2003086604A (ja) * | 2001-09-10 | 2003-03-20 | Advanced Lcd Technologies Development Center Co Ltd | 薄膜半導体装置及びその基板ならびにその製造方法 |
-
2004
- 2004-07-20 FR FR0451589A patent/FR2873491B1/fr not_active Expired - Fee Related
-
2005
- 2005-07-19 US US11/183,993 patent/US7713850B2/en not_active Expired - Fee Related
- 2005-07-19 AT AT05106613T patent/ATE505569T1/de not_active IP Right Cessation
- 2005-07-19 EP EP05106613A patent/EP1619277B1/de not_active Expired - Lifetime
- 2005-07-19 DE DE602005027425T patent/DE602005027425D1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US7713850B2 (en) | 2010-05-11 |
| US20060019459A1 (en) | 2006-01-26 |
| FR2873491A1 (fr) | 2006-01-27 |
| DE602005027425D1 (de) | 2011-05-26 |
| EP1619277B1 (de) | 2011-04-13 |
| FR2873491B1 (fr) | 2006-09-22 |
| EP1619277A3 (de) | 2009-07-08 |
| EP1619277A2 (de) | 2006-01-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |