ATE511674T1 - Verfahren und system zur auflösung gleichzeitig vorgegebener verzweigungsinstruktionen - Google Patents

Verfahren und system zur auflösung gleichzeitig vorgegebener verzweigungsinstruktionen

Info

Publication number
ATE511674T1
ATE511674T1 AT07843403T AT07843403T ATE511674T1 AT E511674 T1 ATE511674 T1 AT E511674T1 AT 07843403 T AT07843403 T AT 07843403T AT 07843403 T AT07843403 T AT 07843403T AT E511674 T1 ATE511674 T1 AT E511674T1
Authority
AT
Austria
Prior art keywords
branch instructions
predicted
given branch
simultaneously given
predicted branch
Prior art date
Application number
AT07843403T
Other languages
English (en)
Inventor
Rodney Wayne Smith
Brian Micheal Stempel
James Norris Dieffenderfer
Thomas Andrew Sartorius
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE511674T1 publication Critical patent/ATE511674T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
AT07843403T 2006-09-27 2007-09-27 Verfahren und system zur auflösung gleichzeitig vorgegebener verzweigungsinstruktionen ATE511674T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/535,536 US7617387B2 (en) 2006-09-27 2006-09-27 Methods and system for resolving simultaneous predicted branch instructions
PCT/US2007/079781 WO2008039947A1 (en) 2006-09-27 2007-09-27 Methods and system for resolving simultaneous predicted branch instructions

Publications (1)

Publication Number Publication Date
ATE511674T1 true ATE511674T1 (de) 2011-06-15

Family

ID=38924371

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07843403T ATE511674T1 (de) 2006-09-27 2007-09-27 Verfahren und system zur auflösung gleichzeitig vorgegebener verzweigungsinstruktionen

Country Status (7)

Country Link
US (2) US7617387B2 (de)
EP (1) EP2069915B1 (de)
JP (2) JP5221546B2 (de)
KR (1) KR101073732B1 (de)
CN (1) CN101523344B (de)
AT (1) ATE511674T1 (de)
WO (1) WO2008039947A1 (de)

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US7617387B2 (en) * 2006-09-27 2009-11-10 Qualcomm Incorporated Methods and system for resolving simultaneous predicted branch instructions
CN102184091A (zh) * 2011-04-18 2011-09-14 孙瑞琛 一种分支预测方法及装置
WO2013100998A1 (en) * 2011-12-28 2013-07-04 Intel Corporation Processor with second jump execution unit for branch misprediction
US20140156977A1 (en) * 2011-12-28 2014-06-05 Mark J. Dechene Enabling and disabling a second jump execution unit for branch misprediction
US9268569B2 (en) * 2012-02-24 2016-02-23 Apple Inc. Branch misprediction behavior suppression on zero predicate branch mispredict
US9411590B2 (en) 2013-03-15 2016-08-09 Qualcomm Incorporated Method to improve speed of executing return branch instructions in a processor
US10108419B2 (en) * 2014-09-26 2018-10-23 Qualcomm Incorporated Dependency-prediction of instructions
US10853076B2 (en) * 2018-02-21 2020-12-01 Arm Limited Performing at least two branch predictions for non-contiguous instruction blocks at the same time using a prediction mapping
US10782976B2 (en) * 2018-05-07 2020-09-22 Dejan Spasov Issuing and flushing instructions from reservation stations using wrap bits and indexes
US12204908B2 (en) * 2018-06-04 2025-01-21 Advanced Micro Devices, Inc. Storing incidental branch predictions to reduce latency of misprediction recovery
US11086629B2 (en) * 2018-11-09 2021-08-10 Arm Limited Misprediction of predicted taken branches in a data processing apparatus
US10846097B2 (en) * 2018-12-20 2020-11-24 Samsung Electronics Co., Ltd. Mispredict recovery apparatus and method for branch and fetch pipelines
US20210149676A1 (en) * 2019-11-14 2021-05-20 Higon Austin R&D Center Corporation Branch Prediction Method, Branch Prediction Unit and Processor Core
CN111459549B (zh) 2020-04-07 2022-11-01 上海兆芯集成电路有限公司 具有高度领先分支预测器的微处理器
CN112256331B (zh) * 2020-12-22 2021-04-27 鹏城实验室 虚拟机指令解析加速方法、装置和计算机存储介质
US11663013B2 (en) 2021-08-24 2023-05-30 International Business Machines Corporation Dependency skipping execution
US11809874B2 (en) * 2022-02-01 2023-11-07 Apple Inc. Conditional instructions distribution and execution on pipelines having different latencies for mispredictions
US12067399B2 (en) 2022-02-01 2024-08-20 Apple Inc. Conditional instructions prediction
KR20240102798A (ko) 2022-12-26 2024-07-03 리벨리온 주식회사 뉴럴 프로세서 및 이의 명령어 페치 방법
US12450068B2 (en) 2023-07-25 2025-10-21 Apple Inc. Biased conditional instruction prediction
US12578965B2 (en) 2023-07-25 2026-03-17 Apple Inc. Biased indirect control transfer prediction

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US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5434985A (en) * 1992-08-11 1995-07-18 International Business Machines Corporation Simultaneous prediction of multiple branches for superscalar processing
JPH0756735A (ja) * 1993-08-16 1995-03-03 Nkk Corp 並列演算処理装置
ES2138051T3 (es) * 1994-01-03 2000-01-01 Intel Corp Metodo y aparato para la realizacion de un sistema de resolucion de bifurcaciones en cuatro etapas en un procesador informatico.
US5586278A (en) * 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
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US5740417A (en) * 1995-12-05 1998-04-14 Motorola, Inc. Pipelined processor operating in different power mode based on branch prediction state of branch history bit encoded as taken weakly not taken and strongly not taken states
US5752014A (en) * 1996-04-29 1998-05-12 International Business Machines Corporation Automatic selection of branch prediction methodology for subsequent branch instruction based on outcome of previous branch prediction
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US7617387B2 (en) * 2006-09-27 2009-11-10 Qualcomm Incorporated Methods and system for resolving simultaneous predicted branch instructions

Also Published As

Publication number Publication date
US7617387B2 (en) 2009-11-10
JP2013122774A (ja) 2013-06-20
KR101073732B1 (ko) 2011-10-13
KR20090061667A (ko) 2009-06-16
EP2069915A1 (de) 2009-06-17
US8082428B2 (en) 2011-12-20
CN101523344B (zh) 2013-01-23
WO2008039947A1 (en) 2008-04-03
US20080077781A1 (en) 2008-03-27
EP2069915B1 (de) 2011-06-01
CN101523344A (zh) 2009-09-02
JP2010505210A (ja) 2010-02-18
US20100023696A1 (en) 2010-01-28
JP5221546B2 (ja) 2013-06-26

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