ATE512464T1 - Kohlenstoff-nanoröhren bondpad-struktur und verfahren zu ihrer herstellung - Google Patents

Kohlenstoff-nanoröhren bondpad-struktur und verfahren zu ihrer herstellung

Info

Publication number
ATE512464T1
ATE512464T1 AT06727747T AT06727747T ATE512464T1 AT E512464 T1 ATE512464 T1 AT E512464T1 AT 06727747 T AT06727747 T AT 06727747T AT 06727747 T AT06727747 T AT 06727747T AT E512464 T1 ATE512464 T1 AT E512464T1
Authority
AT
Austria
Prior art keywords
carbon nanotube
conductive layer
nanotube material
array
vias
Prior art date
Application number
AT06727747T
Other languages
English (en)
Inventor
Chris Wyland
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Application granted granted Critical
Publication of ATE512464T1 publication Critical patent/ATE512464T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4462—Carbon or carbon-containing materials, e.g. graphene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H10W72/9232—Bond pads having multiple stacked layers with additional elements interposed between layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
    • Y10S977/742—Carbon nanotubes, CNTs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
AT06727747T 2005-03-28 2006-03-27 Kohlenstoff-nanoröhren bondpad-struktur und verfahren zu ihrer herstellung ATE512464T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US66603805P 2005-03-28 2005-03-28
PCT/IB2006/050929 WO2006103620A2 (en) 2005-03-28 2006-03-27 Carbon nanotube bond pad srtucture and manufacturing method thereof

Publications (1)

Publication Number Publication Date
ATE512464T1 true ATE512464T1 (de) 2011-06-15

Family

ID=36693219

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06727747T ATE512464T1 (de) 2005-03-28 2006-03-27 Kohlenstoff-nanoröhren bondpad-struktur und verfahren zu ihrer herstellung

Country Status (6)

Country Link
US (1) US7872352B2 (de)
EP (2) EP1866962B1 (de)
CN (1) CN101185164B (de)
AT (1) ATE512464T1 (de)
TW (1) TWI420628B (de)
WO (1) WO2006103620A2 (de)

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US7709962B2 (en) * 2006-10-27 2010-05-04 Infineon Technologies Ag Layout structure having a fill element arranged at an angle to a conducting line
US7612457B2 (en) 2007-06-21 2009-11-03 Infineon Technologies Ag Semiconductor device including a stress buffer
US7862342B2 (en) * 2009-03-18 2011-01-04 Eaton Corporation Electrical interfaces including a nano-particle layer
CN102143652B (zh) * 2010-01-30 2012-07-18 宏恒胜电子科技（淮安）有限公司 电路板
TWI424544B (zh) * 2011-03-31 2014-01-21 聯詠科技股份有限公司 積體電路裝置
US9425331B2 (en) 2014-08-06 2016-08-23 The Boeing Company Solar cell wafer connecting system
US9960130B2 (en) * 2015-02-06 2018-05-01 UTAC Headquarters Pte. Ltd. Reliable interconnect
CN110494983B (zh) * 2017-03-16 2023-09-15 美商艾德亚半导体科技有限责任公司 直接键合的led阵列和应用
KR102821884B1 (ko) 2020-02-27 2025-06-17 삼성전자주식회사 반도체 패키지 장치
TWI853184B (zh) * 2021-08-04 2024-08-21 義守大學 配置三維堆疊晶片間的訊號墊片的方法和電子裝置
CN117059590B (zh) * 2023-10-11 2024-03-12 荣耀终端有限公司 晶圆结构及芯片

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Publication number Priority date Publication date Assignee Title
US5149674A (en) * 1991-06-17 1992-09-22 Motorola, Inc. Method for making a planar multi-layer metal bonding pad
US6146227A (en) * 1998-09-28 2000-11-14 Xidex Corporation Method for manufacturing carbon nanotubes as functional elements of MEMS devices
US7335603B2 (en) * 2000-02-07 2008-02-26 Vladimir Mancevski System and method for fabricating logic devices comprising carbon nanotube transistors
WO2001057917A2 (en) * 2000-02-07 2001-08-09 Xidex Corporation System and method for fabricating logic devices comprising carbon nanotube transistors
KR100360476B1 (ko) * 2000-06-27 2002-11-08 삼성전자 주식회사 탄소나노튜브를 이용한 나노 크기 수직 트랜지스터 및 그제조방법
US6837928B1 (en) * 2001-08-30 2005-01-04 The Board Of Trustees Of The Leland Stanford Junior University Electric field orientation of carbon nanotubes
DE10161312A1 (de) * 2001-12-13 2003-07-10 Infineon Technologies Ag Verfahren zum Herstellen einer Schicht-Anordnung und Schicht-Anordnung
US20030211724A1 (en) * 2002-05-10 2003-11-13 Texas Instruments Incorporated Providing electrical conductivity between an active region and a conductive layer in a semiconductor device using carbon nanotubes
US6933222B2 (en) * 2003-01-02 2005-08-23 Intel Corporation Microcircuit fabrication and interconnection
DE10307815B3 (de) * 2003-02-24 2004-11-11 Infineon Technologies Ag Integriertes elektronisches Bauelement mit gezielt erzeugten Nanoröhren in vertikalen Strukturen und dessen Herstellungsverfahren
US6984579B2 (en) * 2003-02-27 2006-01-10 Applied Materials, Inc. Ultra low k plasma CVD nanotube/spin-on dielectrics with improved properties for advanced nanoelectronic device fabrication
US7018917B2 (en) * 2003-11-20 2006-03-28 Asm International N.V. Multilayer metallization
US7135773B2 (en) * 2004-02-26 2006-11-14 International Business Machines Corporation Integrated circuit chip utilizing carbon nanotube composite interconnection vias
JP4448356B2 (ja) * 2004-03-26 2010-04-07 富士通株式会社 半導体装置およびその製造方法
US7129567B2 (en) * 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
US7229909B2 (en) * 2004-12-09 2007-06-12 International Business Machines Corporation Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes
US7679180B2 (en) 2006-11-07 2010-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad design to minimize dielectric cracking

Also Published As

Publication number Publication date
US20080211112A1 (en) 2008-09-04
TW200711084A (en) 2007-03-16
CN101185164A (zh) 2008-05-21
TWI420628B (zh) 2013-12-21
US7872352B2 (en) 2011-01-18
CN101185164B (zh) 2010-09-01
EP2306514A2 (de) 2011-04-06
WO2006103620A2 (en) 2006-10-05
EP1866962B1 (de) 2011-06-08
EP1866962A2 (de) 2007-12-19
EP2306514A3 (de) 2011-06-22
WO2006103620A3 (en) 2007-01-11

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