ATE513296T1 - Verfahren und vorrichtung zur impliziten dram- vorladung - Google Patents

Verfahren und vorrichtung zur impliziten dram- vorladung

Info

Publication number
ATE513296T1
ATE513296T1 AT04789296T AT04789296T ATE513296T1 AT E513296 T1 ATE513296 T1 AT E513296T1 AT 04789296 T AT04789296 T AT 04789296T AT 04789296 T AT04789296 T AT 04789296T AT E513296 T1 ATE513296 T1 AT E513296T1
Authority
AT
Austria
Prior art keywords
supoint
implied
dram
memory device
command
Prior art date
Application number
AT04789296T
Other languages
English (en)
Inventor
Randy Osborne
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE513296T1 publication Critical patent/ATE513296T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
AT04789296T 2003-09-30 2004-09-29 Verfahren und vorrichtung zur impliziten dram- vorladung ATE513296T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/676,882 US7167946B2 (en) 2003-09-30 2003-09-30 Method and apparatus for implicit DRAM precharge
PCT/US2004/032056 WO2005034133A1 (en) 2003-09-30 2004-09-29 Method and apparatus for implicit dram precharge

Publications (1)

Publication Number Publication Date
ATE513296T1 true ATE513296T1 (de) 2011-07-15

Family

ID=34377477

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04789296T ATE513296T1 (de) 2003-09-30 2004-09-29 Verfahren und vorrichtung zur impliziten dram- vorladung

Country Status (8)

Country Link
US (1) US7167946B2 (de)
EP (1) EP1668646B1 (de)
JP (1) JP4704345B2 (de)
CN (1) CN1853238B (de)
AT (1) ATE513296T1 (de)
RU (1) RU2331118C2 (de)
TW (1) TWI264640B (de)
WO (1) WO2005034133A1 (de)

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US20070130374A1 (en) * 2005-11-15 2007-06-07 Intel Corporation Multiported memory with configurable ports
US20070150667A1 (en) * 2005-12-23 2007-06-28 Intel Corporation Multiported memory with ports mapped to bank sets
US7990737B2 (en) 2005-12-23 2011-08-02 Intel Corporation Memory systems with memory chips down and up
US7673111B2 (en) * 2005-12-23 2010-03-02 Intel Corporation Memory system with both single and consolidated commands
US7698589B2 (en) * 2006-03-21 2010-04-13 Mediatek Inc. Memory controller and device with data strobe calibration
US7349233B2 (en) * 2006-03-24 2008-03-25 Intel Corporation Memory device with read data from different banks
US7761656B2 (en) * 2007-08-22 2010-07-20 Advanced Micro Devices, Inc. Detection of speculative precharge
US8130576B2 (en) * 2008-06-30 2012-03-06 Intel Corporation Memory throughput increase via fine granularity of precharge management
US8601205B1 (en) * 2008-12-31 2013-12-03 Synopsys, Inc. Dynamic random access memory controller
US9042198B2 (en) 2013-03-21 2015-05-26 Yutaka Shirai Nonvolatile random access memory
US9021154B2 (en) * 2013-09-27 2015-04-28 Intel Corporation Read training a memory controller
KR20160016126A (ko) * 2014-08-04 2016-02-15 에스케이하이닉스 주식회사 뱅크 제어 회로 및 이를 포함하는 반도체 메모리 장치
US9600183B2 (en) 2014-09-22 2017-03-21 Intel Corporation Apparatus, system and method for determining comparison information based on memory data
US9530468B2 (en) 2014-09-26 2016-12-27 Intel Corporation Method, apparatus and system to manage implicit pre-charge command signaling
US10497438B2 (en) * 2017-04-14 2019-12-03 Sandisk Technologies Llc Cross-point memory array addressing
US11074949B2 (en) * 2019-07-18 2021-07-27 Micron Technology, Inc. Parallel access for memory subarrays
US11751282B2 (en) * 2020-07-31 2023-09-05 Qualcomm Incorporated Activating sidelink relay MAC-CE
KR102545175B1 (ko) 2022-05-02 2023-06-20 삼성전자주식회사 어드레스 테이블을 포함하는 메모리 장치, 및 메모리 컨트롤러의 동작 방법
CN115308572B (zh) * 2022-08-09 2025-11-07 紫光展讯通信(惠州)有限公司 一种快充充电电路检测方法及相关装置
CN116913343B (zh) * 2023-09-13 2023-12-26 浙江力积存储科技有限公司 一种激活预充电反馈电路和存储器

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US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
RU2047919C1 (ru) * 1991-01-02 1995-11-10 Научно-исследовательский институт специальных информационно-измерительных систем Оперативное запоминающее устройство
JP2988804B2 (ja) * 1993-03-19 1999-12-13 株式会社東芝 半導体メモリ装置
US5539696A (en) * 1994-01-31 1996-07-23 Patel; Vipul C. Method and apparatus for writing data in a synchronous memory having column independent sections and a method and apparatus for performing write mask operations
US5544306A (en) * 1994-05-03 1996-08-06 Sun Microsystems, Inc. Flexible dram access in a frame buffer memory and system
US5634112A (en) * 1994-10-14 1997-05-27 Compaq Computer Corporation Memory controller having precharge prediction based on processor and PCI bus cycles
US6505282B1 (en) * 1994-11-30 2003-01-07 Intel Corporation Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics
USRE36532E (en) * 1995-03-02 2000-01-25 Samsung Electronics Co., Ltd. Synchronous semiconductor memory device having an auto-precharge function
US5636173A (en) * 1995-06-07 1997-06-03 Micron Technology, Inc. Auto-precharge during bank selection
JPH0963264A (ja) * 1995-08-18 1997-03-07 Fujitsu Ltd 同期型ｄｒａｍ
US6145065A (en) * 1997-05-02 2000-11-07 Matsushita Electric Industrial Co., Ltd. Memory access buffer and reordering apparatus using priorities
US6269433B1 (en) * 1998-04-29 2001-07-31 Compaq Computer Corporation Memory controller using queue look-ahead to reduce memory latency
US6378056B2 (en) * 1998-11-03 2002-04-23 Intel Corporation Method and apparatus for configuring a memory device and a memory channel using configuration space registers
US6539440B1 (en) * 1998-11-16 2003-03-25 Infineon Ag Methods and apparatus for prediction of the time between two consecutive memory accesses
US6453370B1 (en) * 1998-11-16 2002-09-17 Infineion Technologies Ag Using of bank tag registers to avoid a background operation collision in memory systems
EP1026595B1 (de) * 1999-01-11 2008-07-23 STMicroelectronics Limited Speicherschnittstellenvorrichtung und Verfahren zum Speicherzugriff
US6330636B1 (en) * 1999-01-29 2001-12-11 Enhanced Memory Systems, Inc. Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank
US6526583B1 (en) * 1999-03-05 2003-02-25 Teralogic, Inc. Interactive set-top box having a unified memory architecture
KR100297193B1 (ko) * 1999-04-27 2001-10-29 윤종용 리던던트 로우 대체 구조를 가지는 반도체 메모리 장치 및 그것의 로우 구동 방법
US6453401B1 (en) * 1999-07-02 2002-09-17 Rambus Inc. Memory controller with timing constraint tracking and checking unit and corresponding method
US6470433B1 (en) * 2000-04-29 2002-10-22 Hewlett-Packard Company Modified aggressive precharge DRAM controller
US6535966B1 (en) * 2000-05-17 2003-03-18 Sun Microsystems, Inc. System and method for using a page tracking buffer to reduce main memory latency in a computer system
US6477108B2 (en) * 2000-09-01 2002-11-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including memory with reduced current consumption
US6747912B1 (en) * 2002-12-31 2004-06-08 Intel Corporation Implied precharge and posted activate command to reduce command bandwidth

Also Published As

Publication number Publication date
EP1668646B1 (de) 2011-06-15
JP2007507831A (ja) 2007-03-29
TWI264640B (en) 2006-10-21
EP1668646A1 (de) 2006-06-14
US20050071541A1 (en) 2005-03-31
CN1853238B (zh) 2010-05-05
TW200521674A (en) 2005-07-01
CN1853238A (zh) 2006-10-25
JP4704345B2 (ja) 2011-06-15
RU2006114769A (ru) 2007-11-20
RU2331118C2 (ru) 2008-08-10
WO2005034133A1 (en) 2005-04-14
US7167946B2 (en) 2007-01-23

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