ATE514982T1 - Verfahren und vorrichtungen zur auswertung regulärer ausdrücke beliebiger grösse - Google Patents

Verfahren und vorrichtungen zur auswertung regulärer ausdrücke beliebiger grösse

Info

Publication number
ATE514982T1
ATE514982T1 AT04701191T AT04701191T ATE514982T1 AT E514982 T1 ATE514982 T1 AT E514982T1 AT 04701191 T AT04701191 T AT 04701191T AT 04701191 T AT04701191 T AT 04701191T AT E514982 T1 ATE514982 T1 AT E514982T1
Authority
AT
Austria
Prior art keywords
states
implemented
building block
building blocks
programmable
Prior art date
Application number
AT04701191T
Other languages
English (en)
Inventor
Harshvardhan Sharangpani
Rajesh Patil
Manoj Khare
Kent Fielden
Judge Kennedy Arora
Original Assignee
Cisco Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cisco Tech Inc filed Critical Cisco Tech Inc
Priority claimed from PCT/US2004/000435 external-priority patent/WO2004063886A2/en
Application granted granted Critical
Publication of ATE514982T1 publication Critical patent/ATE514982T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90Details of database functions independent of the retrieved data types
    • G06F16/903Querying
    • G06F16/90335Query processing
    • G06F16/90344Query processing by using string matching techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Devices For Executing Special Programs (AREA)
  • Debugging And Monitoring (AREA)
  • Stored Programmes (AREA)
AT04701191T 2003-01-09 2004-01-09 Verfahren und vorrichtungen zur auswertung regulärer ausdrücke beliebiger grösse ATE514982T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US43884703P 2003-01-09 2003-01-09
US10/755,048 US7085918B2 (en) 2003-01-09 2004-01-08 Methods and apparatuses for evaluation of regular expressions of arbitrary size
PCT/US2004/000435 WO2004063886A2 (en) 2003-01-09 2004-01-09 Methods and apparatuses for evaluation of regular expressions of arbitrary size

Publications (1)

Publication Number Publication Date
ATE514982T1 true ATE514982T1 (de) 2011-07-15

Family

ID=36704027

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04701191T ATE514982T1 (de) 2003-01-09 2004-01-09 Verfahren und vorrichtungen zur auswertung regulärer ausdrücke beliebiger grösse

Country Status (6)

Country Link
US (1) US7085918B2 (de)
EP (1) EP1581841B1 (de)
CN (1) CN100511049C (de)
AT (1) ATE514982T1 (de)
AU (1) AU2004204933B2 (de)
CA (1) CA2512862C (de)

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US7934255B1 (en) * 2005-11-08 2011-04-26 Nvidia Corporation Apparatus, system, and method for offloading packet classification
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US7890692B2 (en) * 2007-08-17 2011-02-15 Pandya Ashish A FSA context switch architecture for programmable intelligent search memory
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US9083740B1 (en) * 2009-09-28 2015-07-14 Juniper Networks, Inc. Network traffic pattern matching using adaptive deterministic finite automata
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US9268881B2 (en) 2012-10-19 2016-02-23 Intel Corporation Child state pre-fetch in NFAs
US9117170B2 (en) 2012-11-19 2015-08-25 Intel Corporation Complex NFA state matching method that matches input symbols against character classes (CCLs), and compares sequence CCLs in parallel
US9665664B2 (en) 2012-11-26 2017-05-30 Intel Corporation DFA-NFA hybrid
US9304768B2 (en) 2012-12-18 2016-04-05 Intel Corporation Cache prefetch for deterministic finite automaton instructions
US9251440B2 (en) * 2012-12-18 2016-02-02 Intel Corporation Multiple step non-deterministic finite automaton matching
US9268570B2 (en) 2013-01-23 2016-02-23 Intel Corporation DFA compression and execution
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Also Published As

Publication number Publication date
EP1581841A2 (de) 2005-10-05
CA2512862A1 (en) 2004-07-29
CN1759354A (zh) 2006-04-12
AU2004204933B2 (en) 2008-11-06
EP1581841B1 (de) 2011-06-29
US7085918B2 (en) 2006-08-01
AU2004204933A1 (en) 2004-07-29
CA2512862C (en) 2009-03-17
US20050012521A1 (en) 2005-01-20
CN100511049C (zh) 2009-07-08

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