ATE514998T1 - Getaktete ports - Google Patents

Getaktete ports

Info

Publication number
ATE514998T1
ATE514998T1 AT08736222T AT08736222T ATE514998T1 AT E514998 T1 ATE514998 T1 AT E514998T1 AT 08736222 T AT08736222 T AT 08736222T AT 08736222 T AT08736222 T AT 08736222T AT E514998 T1 ATE514998 T1 AT E514998T1
Authority
AT
Austria
Prior art keywords
dependence
timing signal
port
threads
execution
Prior art date
Application number
AT08736222T
Other languages
English (en)
Inventor
Michael David May
Peter Hedinger
Alastair Dixon
Original Assignee
Xmos Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xmos Ltd filed Critical Xmos Ltd
Application granted granted Critical
Publication of ATE514998T1 publication Critical patent/ATE514998T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/405Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009Thread control instructions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Executing Machine-Instructions (AREA)
AT08736222T 2007-04-17 2008-04-15 Getaktete ports ATE514998T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/785,345 US7613909B2 (en) 2007-04-17 2007-04-17 Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor
PCT/EP2008/054528 WO2008125669A1 (en) 2007-04-17 2008-04-15 Clocked ports

Publications (1)

Publication Number Publication Date
ATE514998T1 true ATE514998T1 (de) 2011-07-15

Family

ID=39591132

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08736222T ATE514998T1 (de) 2007-04-17 2008-04-15 Getaktete ports

Country Status (4)

Country Link
US (1) US7613909B2 (de)
EP (1) EP2137628B1 (de)
AT (1) ATE514998T1 (de)
WO (1) WO2008125669A1 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8447960B2 (en) * 2010-01-08 2013-05-21 International Business Machines Corporation Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition
US20110173420A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Processor resume unit
US10157060B2 (en) * 2011-12-29 2018-12-18 Intel Corporation Method, device and system for control signaling in a data path module of a data stream processing engine
US8631370B2 (en) 2012-04-26 2014-01-14 International Business Machines Corporation Swapping ports to change the timing window overlap of adjacent nets
US10331583B2 (en) 2013-09-26 2019-06-25 Intel Corporation Executing distributed memory operations using processing elements connected by distributed channels
US10402168B2 (en) 2016-10-01 2019-09-03 Intel Corporation Low energy consumption mantissa multiplication for floating point multiply-add operations
US10416999B2 (en) 2016-12-30 2019-09-17 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10572376B2 (en) 2016-12-30 2020-02-25 Intel Corporation Memory ordering in acceleration hardware
US10474375B2 (en) 2016-12-30 2019-11-12 Intel Corporation Runtime address disambiguation in acceleration hardware
US10558575B2 (en) 2016-12-30 2020-02-11 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10515046B2 (en) 2017-07-01 2019-12-24 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
US10445451B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features
US10469397B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods with configurable network-based dataflow operator circuits
US10467183B2 (en) 2017-07-01 2019-11-05 Intel Corporation Processors and methods for pipelined runtime services in a spatial array
US10387319B2 (en) 2017-07-01 2019-08-20 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features
US10445234B2 (en) 2017-07-01 2019-10-15 Intel Corporation Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features
US10515049B1 (en) 2017-07-01 2019-12-24 Intel Corporation Memory circuits and methods for distributed memory hazard detection and error recovery
US10496574B2 (en) 2017-09-28 2019-12-03 Intel Corporation Processors, methods, and systems for a memory fence in a configurable spatial accelerator
US11086816B2 (en) 2017-09-28 2021-08-10 Intel Corporation Processors, methods, and systems for debugging a configurable spatial accelerator
US10380063B2 (en) 2017-09-30 2019-08-13 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator having a sequencer dataflow operator
US10445098B2 (en) 2017-09-30 2019-10-15 Intel Corporation Processors and methods for privileged configuration in a spatial array
US10565134B2 (en) 2017-12-30 2020-02-18 Intel Corporation Apparatus, methods, and systems for multicast in a configurable spatial accelerator
US10445250B2 (en) 2017-12-30 2019-10-15 Intel Corporation Apparatus, methods, and systems with a configurable spatial accelerator
US10417175B2 (en) 2017-12-30 2019-09-17 Intel Corporation Apparatus, methods, and systems for memory consistency in a configurable spatial accelerator
US10564980B2 (en) 2018-04-03 2020-02-18 Intel Corporation Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator
US11307873B2 (en) 2018-04-03 2022-04-19 Intel Corporation Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging
US10853073B2 (en) 2018-06-30 2020-12-01 Intel Corporation Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
US10459866B1 (en) 2018-06-30 2019-10-29 Intel Corporation Apparatuses, methods, and systems for integrated control and data processing in a configurable spatial accelerator
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US10891240B2 (en) 2018-06-30 2021-01-12 Intel Corporation Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator
US10678724B1 (en) 2018-12-29 2020-06-09 Intel Corporation Apparatuses, methods, and systems for in-network storage in a configurable spatial accelerator
US10817291B2 (en) 2019-03-30 2020-10-27 Intel Corporation Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator
US10965536B2 (en) 2019-03-30 2021-03-30 Intel Corporation Methods and apparatus to insert buffers in a dataflow graph
US10915471B2 (en) 2019-03-30 2021-02-09 Intel Corporation Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator
US11029927B2 (en) 2019-03-30 2021-06-08 Intel Corporation Methods and apparatus to detect and annotate backedges in a dataflow graph
US11037050B2 (en) 2019-06-29 2021-06-15 Intel Corporation Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator
US11288072B2 (en) * 2019-09-11 2022-03-29 Ceremorphic, Inc. Multi-threaded processor with thread granularity
US11907713B2 (en) 2019-12-28 2024-02-20 Intel Corporation Apparatuses, methods, and systems for fused operations using sign modification in a processing element of a configurable spatial accelerator
US12086080B2 (en) 2020-09-26 2024-09-10 Intel Corporation Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592488A (en) * 1995-06-07 1997-01-07 Micron Technology, Inc. Method and apparatus for pipelined multiplexing employing analog delays for a multiport interface
US6661794B1 (en) * 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US7765547B2 (en) 2004-11-24 2010-07-27 Maxim Integrated Products, Inc. Hardware multithreading systems with state registers having thread profiling data
US7457246B2 (en) * 2004-12-22 2008-11-25 Intel Corporation Adaptive threads assignment for receiving packets
US7454538B2 (en) * 2005-05-11 2008-11-18 Qualcomm Incorporated Latency insensitive FIFO signaling protocol

Also Published As

Publication number Publication date
US20080263330A1 (en) 2008-10-23
EP2137628A1 (de) 2009-12-30
WO2008125669A1 (en) 2008-10-23
US7613909B2 (en) 2009-11-03
EP2137628B1 (de) 2011-06-29

Similar Documents

Publication Publication Date Title
ATE514998T1 (de) Getaktete ports
WO2010068855A3 (en) Apparatus and methods for adaptive thread scheduling on asymmetric multiprocessor
IN2012DN02726A (de)
GB2492205A (en) Querying performance data on a parallel computer system having compute nodes
IN2012DN00929A (de)
GB201303285D0 (en) Application scheduling in hetrogeneous multiprocessor computing platforms
GB2485682A (en) Mapping of computer threads onto heterogeneous resources
EP2778907A3 (de) Parallelisierung von Schleifen in Anwesenheit möglicher Speicher-Aliasnamen
WO2010043401A3 (en) Sequential processor comprising an alu array
ATE447740T1 (de) Dynamisch erzeugtes betriebssystem für sensorennetze
GB2492672A (en) Reducing latency in serializer-deserializer links
WO2009037731A1 (ja) 翻訳装置と翻訳方法および翻訳プログラムとプロセッサコアの制御方法およびプロセッサ
GB2485683A (en) Thread shift: Allocating threads to cores
EP2192536A3 (de) Integrierte Designanwendung
TW201614493A (en) Sharing resources between a CPU and GPU
EA201390868A1 (ru) Способ и система для вычислительного ускорения обработки сейсмических данных
JP2010181989A5 (de)
JP2012525620A5 (de)
GB201014318D0 (en) Improved processor architecture
GB201211273D0 (en) Multilevel cache system
GB201121272D0 (en) Processor communication
GB2474983A (en) DMA engine
WO2007008519A3 (en) Active element machine computation
WO2012009150A3 (en) Direct memory access engine physical memory descriptors for multi-media demultiplexing operations
Leyvand et al. A unified approach for scheduling with convex resource consumption functions using positional penalties

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties