ATE515708T1 - Testsimulator für integrierte schaltkreise - Google Patents

Testsimulator für integrierte schaltkreise

Info

Publication number
ATE515708T1
ATE515708T1 AT06122129T AT06122129T ATE515708T1 AT E515708 T1 ATE515708 T1 AT E515708T1 AT 06122129 T AT06122129 T AT 06122129T AT 06122129 T AT06122129 T AT 06122129T AT E515708 T1 ATE515708 T1 AT E515708T1
Authority
AT
Austria
Prior art keywords
simulator
integrated circuit
circuit test
test simulator
conditions
Prior art date
Application number
AT06122129T
Other languages
English (en)
Inventor
Assche Gilles Van
Jean-Louis Modave
Original Assignee
Proton World Int Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Proton World Int Nv filed Critical Proton World Int Nv
Application granted granted Critical
Publication of ATE515708T1 publication Critical patent/ATE515708T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT06122129T 2005-10-12 2006-10-11 Testsimulator für integrierte schaltkreise ATE515708T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0553105 2005-10-12

Publications (1)

Publication Number Publication Date
ATE515708T1 true ATE515708T1 (de) 2011-07-15

Family

ID=36636352

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06122129T ATE515708T1 (de) 2005-10-12 2006-10-11 Testsimulator für integrierte schaltkreise

Country Status (3)

Country Link
US (1) US20070083351A1 (de)
EP (1) EP1775595B1 (de)
AT (1) ATE515708T1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2910657B1 (fr) * 2006-12-22 2012-11-16 Ingenico Sa Procede de verification de conformite d'une plateforme electronique et/ou d'un programme informatique present sur cette plateforme, dispositif et programme d'ordinateur correspondants.
US8886507B2 (en) 2011-07-13 2014-11-11 General Electric Company Methods and systems for simulating circuit operation
CN113514759B (zh) 2021-09-07 2021-12-17 南京宏泰半导体科技有限公司 一种多核测试处理器及集成电路测试系统与方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2982741B2 (ja) * 1997-05-13 1999-11-29 日本電気株式会社 集積回路の故障診断装置及びその記録媒体
US6182258B1 (en) * 1997-06-03 2001-01-30 Verisity Ltd. Method and apparatus for test generation during circuit design
FR2766942B1 (fr) * 1997-07-31 1999-10-01 Gemplus Card Int Lecteur de carte a puce avec microcontroleur et composant de securite
US6295623B1 (en) * 1999-01-29 2001-09-25 Credence Systems Corporation System for testing real and simulated versions of an integrated circuit
US6400173B1 (en) * 1999-11-19 2002-06-04 Hitachi, Ltd. Test system and manufacturing of semiconductor device
US6466007B1 (en) * 2000-08-14 2002-10-15 Teradyne, Inc. Test system for smart card and indentification devices and the like
US20030025490A1 (en) * 2001-08-02 2003-02-06 Tzu-Pei Chen Method for verifying hardware circuits through simulation
US7526422B1 (en) * 2001-11-13 2009-04-28 Cypress Semiconductor Corporation System and a method for checking lock-step consistency between an in circuit emulation and a microcontroller
US6775798B2 (en) * 2001-11-28 2004-08-10 Lsi Logic Corporation Fast sampling test bench
JP2003240823A (ja) * 2002-02-15 2003-08-27 Mitsubishi Electric Corp プログラム変換方法、プログラム変換システム、プログラム変換プログラム、治具の設計システム、冶具の設計プログラムおよびプログラムが記録された記録媒体
FR2843214B1 (fr) * 2002-07-30 2008-07-04 Bull Sa Procede de verification fonctionnelle d'un modele de circuit integre pour constituer une plate-forme de verification, equipement emulateur et plate-forme de verification.
JP3833982B2 (ja) * 2002-10-03 2006-10-18 株式会社東芝 テストパターン選択装置、テストパターン選択方法、及びテストパターン選択プログラム
DE10328237A1 (de) * 2003-06-24 2005-01-20 Giesecke & Devrient Gmbh Verfahren zum Erzeugen von Testdaten zum Austesten der Funktionsfähigkeit einer datenverarbeitenden Schaltung
US7340661B2 (en) * 2003-09-25 2008-03-04 Hitachi Global Storage Technologies Netherlands B.V. Computer program product for performing testing of a simulated storage device within a testing simulation environment
US7437692B2 (en) * 2003-11-10 2008-10-14 Infineon Technologies Ag Memory debugger for system-on-a-chip designs
US7007251B2 (en) * 2003-11-12 2006-02-28 International Business Machines Corporation Database mining system and method for coverage analysis of functional verification of integrated circuit designs
US7137083B2 (en) * 2004-04-01 2006-11-14 Verigy Ipco Verification of integrated circuit tests using test simulation and integrated circuit simulation with simulated failure
EP1603043A2 (de) * 2004-06-02 2005-12-07 Proton World International N.V. Verfahren und Vorrichtung zum Testen der Unteilbarkeit von Befehlen in einem Mikroprozessor
US20050289398A1 (en) * 2004-06-24 2005-12-29 Tiw Lee F Testing method and system including processing of simulation data and test patterns
US7562001B2 (en) * 2005-07-29 2009-07-14 International Business Machines Corporation Creating a behavioral model of a hardware device for use in a simulation environment

Also Published As

Publication number Publication date
US20070083351A1 (en) 2007-04-12
EP1775595B1 (de) 2011-07-06
EP1775595A1 (de) 2007-04-18

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Legal Events

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