ATE516533T1 - System mit mehreren prozessoren und verfahren zu seinem betrieb - Google Patents

System mit mehreren prozessoren und verfahren zu seinem betrieb

Info

Publication number
ATE516533T1
ATE516533T1 AT08767909T AT08767909T ATE516533T1 AT E516533 T1 ATE516533 T1 AT E516533T1 AT 08767909 T AT08767909 T AT 08767909T AT 08767909 T AT08767909 T AT 08767909T AT E516533 T1 ATE516533 T1 AT E516533T1
Authority
AT
Austria
Prior art keywords
state
variables
interrupt
processor
buffer memory
Prior art date
Application number
AT08767909T
Other languages
English (en)
Inventor
Uwe Kranich
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE516533T1 publication Critical patent/ATE516533T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
    • G06F9/3879Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043LOAD or STORE instructions; Clear instruction
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087Synchronisation or serialisation instructions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009Thread control instructions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30189Instruction operation extension or modification according to execution mode, e.g. mode flag
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Electrotherapy Devices (AREA)
  • Control Of Eletrric Generators (AREA)
AT08767909T 2007-05-31 2008-05-28 System mit mehreren prozessoren und verfahren zu seinem betrieb ATE516533T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102007025397A DE102007025397B4 (de) 2007-05-31 2007-05-31 System mit mehreren Prozessoren und Verfahren zu seinem Betrieb
US12/014,868 US7689809B2 (en) 2007-05-31 2008-01-16 Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating system
PCT/US2008/006744 WO2008153797A1 (en) 2007-05-31 2008-05-28 System comprising a plurality of processors and methods of operating the same

Publications (1)

Publication Number Publication Date
ATE516533T1 true ATE516533T1 (de) 2011-07-15

Family

ID=39917349

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08767909T ATE516533T1 (de) 2007-05-31 2008-05-28 System mit mehreren prozessoren und verfahren zu seinem betrieb

Country Status (10)

Country Link
US (1) US7689809B2 (de)
EP (1) EP2171575B1 (de)
JP (1) JP5295228B2 (de)
KR (1) KR101485068B1 (de)
CN (1) CN101730881B (de)
AT (1) ATE516533T1 (de)
DE (1) DE102007025397B4 (de)
GB (1) GB2461841A (de)
TW (1) TWI467490B (de)
WO (1) WO2008153797A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100138575A1 (en) * 2008-12-01 2010-06-03 Micron Technology, Inc. Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices
US7930519B2 (en) * 2008-12-17 2011-04-19 Advanced Micro Devices, Inc. Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit
JP4572259B1 (ja) * 2009-04-27 2010-11-04 株式会社フォティーンフォティ技術研究所 情報機器、プログラム及び不正なプログラムコードの実行防止方法
CN101882098B (zh) * 2009-07-10 2012-07-11 威盛电子股份有限公司 微处理器集成电路以及相关除错方法
US9436475B2 (en) * 2012-11-05 2016-09-06 Nvidia Corporation System and method for executing sequential code using a group of threads and single-instruction, multiple-thread processor incorporating the same
US20160147536A1 (en) * 2014-11-24 2016-05-26 International Business Machines Corporation Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two Modes
US9747108B2 (en) * 2015-03-27 2017-08-29 Intel Corporation User-level fork and join processors, methods, systems, and instructions
US20170090927A1 (en) * 2015-09-30 2017-03-30 Paul Caprioli Control transfer instructions indicating intent to call or return
EP3433985B1 (de) * 2016-03-23 2021-01-27 Clavister AB Verfahren zur verkehrsformung mittels eines seriellen paketverarbeitungsalgorithmus und paralleler paketverarbeitungsalgorithmus
US10924416B2 (en) 2016-03-23 2021-02-16 Clavister Ab Method for traffic shaping using a serial packet processing algorithm and a parallel packet processing algorithm
US10541868B2 (en) * 2017-02-24 2020-01-21 Quanta Computer Inc. System and method for automatically updating bios setup options
US12393399B2 (en) 2018-11-06 2025-08-19 International Business Machines Corporation Controlling storage accesses for merge operations
US10831503B2 (en) 2018-11-06 2020-11-10 International Business Machines Corporation Saving and restoring machine state between multiple executions of an instruction
US10831502B2 (en) * 2018-11-06 2020-11-10 International Business Machines Corporation Migration of partially completed instructions
US10831478B2 (en) 2018-11-06 2020-11-10 International Business Machines Corporation Sort and merge instruction for a general-purpose processor
CN111181169B (zh) * 2020-01-13 2023-10-20 深圳市禾望电气股份有限公司 Svg并联运行系统的控制方法、装置以及存储介质
CN114050965B (zh) 2020-07-22 2024-12-03 中兴通讯股份有限公司 查找中断设备的方法、从设备、主设备及存储介质
CN113094111B (zh) * 2021-04-16 2024-01-09 三星(中国)半导体有限公司 设备以及设备的启动方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5197138A (en) 1989-12-26 1993-03-23 Digital Equipment Corporation Reporting delayed coprocessor exceptions to code threads having caused the exceptions by saving and restoring exception state during code thread switching
US5481719A (en) * 1994-09-09 1996-01-02 International Business Machines Corporation Exception handling method and apparatus for a microkernel data processing system
US5812823A (en) 1996-01-02 1998-09-22 International Business Machines Corporation Method and system for performing an emulation context save and restore that is transparent to the operating system
US6003129A (en) * 1996-08-19 1999-12-14 Samsung Electronics Company, Ltd. System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture
US6058465A (en) * 1996-08-19 2000-05-02 Nguyen; Le Trong Single-instruction-multiple-data processing in a multimedia signal processor
US6230259B1 (en) 1997-10-31 2001-05-08 Advanced Micro Devices, Inc. Transparent extended state save
US6574725B1 (en) * 1999-11-01 2003-06-03 Advanced Micro Devices, Inc. Method and mechanism for speculatively executing threads of instructions
US6651163B1 (en) 2000-03-08 2003-11-18 Advanced Micro Devices, Inc. Exception handling with reduced overhead in a multithreaded multiprocessing system
KR100456630B1 (ko) * 2001-12-11 2004-11-10 한국전자통신연구원 프로세서간 통신을 위한 인터럽트 중계 장치 및 방법
US7765388B2 (en) * 2003-09-17 2010-07-27 Broadcom Corporation Interrupt verification support mechanism
JP4457047B2 (ja) * 2005-06-22 2010-04-28 株式会社ルネサステクノロジ マルチプロセッサシステム
US7386646B2 (en) * 2005-08-25 2008-06-10 Broadcom Corporation System and method for interrupt distribution in a multithread processor
US7912302B2 (en) * 2006-09-21 2011-03-22 Analog Devices, Inc. Multiprocessor decoder system and method

Also Published As

Publication number Publication date
KR101485068B1 (ko) 2015-01-21
KR20100036279A (ko) 2010-04-07
EP2171575B1 (de) 2011-07-13
CN101730881B (zh) 2014-07-09
JP5295228B2 (ja) 2013-09-18
GB0920863D0 (en) 2010-01-13
US20080301408A1 (en) 2008-12-04
JP2010529533A (ja) 2010-08-26
DE102007025397B4 (de) 2010-07-15
US7689809B2 (en) 2010-03-30
TW200905566A (en) 2009-02-01
WO2008153797A1 (en) 2008-12-18
EP2171575A1 (de) 2010-04-07
TWI467490B (zh) 2015-01-01
CN101730881A (zh) 2010-06-09
DE102007025397A1 (de) 2008-12-04
GB2461841A (en) 2010-01-20

Similar Documents

Publication Publication Date Title
ATE516533T1 (de) System mit mehreren prozessoren und verfahren zu seinem betrieb
WO2004114128A3 (en) Instruction controlled data processing device
TW200712875A (en) Method for fast switching between different operating systems in computer device with multiple operating systems
DE602005025677D1 (de) Programmierbare datenverarbeitungsschaltung, die simd-befehle unterstützt
WO2007002801A3 (en) System and method of controlling power in a multi-threaded processor
JPWO2008099931A1 (ja) マイクロコンピュータの模擬装置
CN105511919B (zh) 一种可重构系统的动态局部重构控制器及其控制方法
TW200636569A (en) Method for providing an auxiliary bios code utilizing time expiry control, and related device
WO2015183268A1 (en) Voltage selectors coupled to processor cores
JP2009043044A5 (de)
CN104391563B (zh) 一种寄存器堆的循环缓冲电路及其方法,处理器装置
US7954103B2 (en) Method for preventing process collision of micro controller
JP2011197869A (ja) 仮想マルチプロセッサシステム
JP4670574B2 (ja) キースキャン回路
CN101847132A (zh) 一种实现串行flash存储器和开关复用i/o线的方法和密钥装置
JP2014160393A (ja) マイクロプロセッサ及び演算処理方法
CN203838510U (zh) 功能电路及其驱动程序关联系统
JP5166343B2 (ja) 3次元コンピュータグラフィック用プロセッサ
JP2008225710A (ja) コンピュータシステム及び該システムで用いられるプロセス切替え方法
CN100587654C (zh) 省电型数据处理器
CN109948785B (zh) 一种高效的神经网络电路系统和方法
CN102591719A (zh) 一种基于8051cpu系统的中断扩展方法
ATE373845T1 (de) Dmac-ausgabemechanismus über ein steaming-id- verfahren
CN116820588A (zh) 一种主从架构可切换的cpu系统、切换方法及存储介质
JP2015014833A (ja) 再構築可能なlsi

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties