ATE517431T1 - Verfahren zur herstellung eineshalbleiterbauelements mit mos-transistoren mit gate-elektroden, die in einempaket von aufeinander abgelagerten metallschichten ausgebildet sind - Google Patents

Verfahren zur herstellung eineshalbleiterbauelements mit mos-transistoren mit gate-elektroden, die in einempaket von aufeinander abgelagerten metallschichten ausgebildet sind

Info

Publication number
ATE517431T1
ATE517431T1 AT04702397T AT04702397T ATE517431T1 AT E517431 T1 ATE517431 T1 AT E517431T1 AT 04702397 T AT04702397 T AT 04702397T AT 04702397 T AT04702397 T AT 04702397T AT E517431 T1 ATE517431 T1 AT E517431T1
Authority
AT
Austria
Prior art keywords
metal
layer
gate electrodes
semiconductor device
metal layers
Prior art date
Application number
AT04702397T
Other languages
English (en)
Inventor
Robert Lander
Jacob Hooker
Robertus Wolters
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE517431T1 publication Critical patent/ATE517431T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01316—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/669—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
AT04702397T 2003-02-03 2004-01-15 Verfahren zur herstellung eineshalbleiterbauelements mit mos-transistoren mit gate-elektroden, die in einempaket von aufeinander abgelagerten metallschichten ausgebildet sind ATE517431T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03100216 2003-02-03
PCT/IB2004/050027 WO2004070833A1 (en) 2003-02-03 2004-01-15 Method of manufacturing a semiconductor device with mos transistors comprising gate electrodes formed in a packet of metal layers deposited upon one another

Publications (1)

Publication Number Publication Date
ATE517431T1 true ATE517431T1 (de) 2011-08-15

Family

ID=32842800

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04702397T ATE517431T1 (de) 2003-02-03 2004-01-15 Verfahren zur herstellung eineshalbleiterbauelements mit mos-transistoren mit gate-elektroden, die in einempaket von aufeinander abgelagerten metallschichten ausgebildet sind

Country Status (7)

Country Link
US (1) US7326631B2 (de)
EP (1) EP1593154B1 (de)
JP (1) JP2006518106A (de)
KR (1) KR20050094474A (de)
AT (1) ATE517431T1 (de)
TW (1) TW200503172A (de)
WO (1) WO2004070833A1 (de)

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US6872613B1 (en) * 2003-09-04 2005-03-29 Advanced Micro Devices, Inc. Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure
US7291527B2 (en) 2005-09-07 2007-11-06 Texas Instruments Incorporated Work function control of metals
JP2007157739A (ja) * 2005-11-30 2007-06-21 Fujitsu Ltd Ｃｍｏｓ半導体素子とその製造方法
JP4855419B2 (ja) * 2005-12-13 2012-01-18 富士通株式会社 半導体装置の製造方法
JP4828982B2 (ja) * 2006-03-28 2011-11-30 富士通セミコンダクター株式会社 半導体装置の製造方法
KR100775965B1 (ko) 2006-08-17 2007-11-15 삼성전자주식회사 모스 트랜지스터 및 그 제조 방법
JP5011921B2 (ja) * 2006-09-29 2012-08-29 富士通セミコンダクター株式会社 半導体集積回路装置及びその製造方法
US8034678B2 (en) * 2008-01-17 2011-10-11 Kabushiki Kaisha Toshiba Complementary metal oxide semiconductor device fabrication method
CN101981688B (zh) * 2008-04-02 2014-04-02 Imec公司 制造半导体器件的方法以及半导体器件
JP5769160B2 (ja) * 2008-10-30 2015-08-26 国立大学法人東北大学 コンタクト形成方法、半導体装置の製造方法、および半導体装置
WO2012086102A1 (ja) * 2010-12-24 2012-06-28 パナソニック株式会社 半導体装置及びその製造方法
US9443984B2 (en) 2010-12-28 2016-09-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN103854982B (zh) * 2012-11-30 2016-09-28 中国科学院微电子研究所 半导体器件的制造方法
KR102262887B1 (ko) 2014-07-21 2021-06-08 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9831301B1 (en) * 2016-09-19 2017-11-28 International Business Machines Corporation Metal resistor structures with nitrogen content
CN116130417B (zh) * 2022-09-07 2026-02-13 长鑫存储技术有限公司 半导体结构及其制造方法

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DE3003285A1 (de) * 1980-01-30 1981-08-06 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen niederohmiger, einkristalliner metall- oder legierungsschichten auf substraten
JPS6213035A (ja) * 1985-07-11 1987-01-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5668040A (en) * 1995-03-20 1997-09-16 Lg Semicon Co., Ltd. Method for forming a semiconductor device electrode which also serves as a diffusion barrier
US6027961A (en) * 1998-06-30 2000-02-22 Motorola, Inc. CMOS semiconductor devices and method of formation
US6162713A (en) * 1999-06-17 2000-12-19 United Microelectronics Corp. Method for fabricating semiconductor structures having metal silicides
JP2001217323A (ja) * 1999-12-16 2001-08-10 Texas Instr Inc <Ti> Ｃｍｏｓデバイス二重金属ゲート構造作製方法
US6509254B1 (en) * 2000-01-20 2003-01-21 Matsushita Electric Industrial Co., Ltd. Method of forming electrode structure and method of fabricating semiconductor device
JP3613113B2 (ja) 2000-01-21 2005-01-26 日本電気株式会社 半導体装置およびその製造方法
US6451690B1 (en) * 2000-03-13 2002-09-17 Matsushita Electronics Corporation Method of forming electrode structure and method of fabricating semiconductor device
JP3305301B2 (ja) * 2000-08-02 2002-07-22 松下電器産業株式会社 電極構造体の形成方法及び半導体装置の製造方法
JP2002198441A (ja) * 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
US6794234B2 (en) * 2002-01-30 2004-09-21 The Regents Of The University Of California Dual work function CMOS gate technology based on metal interdiffusion
US6872613B1 (en) * 2003-09-04 2005-03-29 Advanced Micro Devices, Inc. Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure

Also Published As

Publication number Publication date
US20060134848A1 (en) 2006-06-22
KR20050094474A (ko) 2005-09-27
EP1593154B1 (de) 2011-07-20
TW200503172A (en) 2005-01-16
JP2006518106A (ja) 2006-08-03
WO2004070833A1 (en) 2004-08-19
EP1593154A1 (de) 2005-11-09
US7326631B2 (en) 2008-02-05
WO2004070833A8 (en) 2005-08-25

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