ATE518248T1 - Verfahren zur herstellung einer nichtflüchtigen speicherzelle mit einem seitlichen auswahl-gate - Google Patents
Verfahren zur herstellung einer nichtflüchtigen speicherzelle mit einem seitlichen auswahl-gateInfo
- Publication number
- ATE518248T1 ATE518248T1 AT04710959T AT04710959T ATE518248T1 AT E518248 T1 ATE518248 T1 AT E518248T1 AT 04710959 T AT04710959 T AT 04710959T AT 04710959 T AT04710959 T AT 04710959T AT E518248 T1 ATE518248 T1 AT E518248T1
- Authority
- AT
- Austria
- Prior art keywords
- stack
- layer
- gate layer
- producing
- memory cell
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
- H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/031—Manufacture or treatment of data-storage electrodes
- H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP03100469 | 2003-02-26 | ||
| PCT/IB2004/050113 WO2004077498A2 (en) | 2003-02-26 | 2004-02-13 | Method of manufacturing a non-volatile memory cell with a lateral select gate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE518248T1 true ATE518248T1 (de) | 2011-08-15 |
Family
ID=32921606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT04710959T ATE518248T1 (de) | 2003-02-26 | 2004-02-13 | Verfahren zur herstellung einer nichtflüchtigen speicherzelle mit einem seitlichen auswahl-gate |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7429513B2 (de) |
| EP (1) | EP1599908B1 (de) |
| JP (1) | JP2006519491A (de) |
| AT (1) | ATE518248T1 (de) |
| WO (1) | WO2004077498A2 (de) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7595528B2 (en) * | 2004-03-10 | 2009-09-29 | Nanosys, Inc. | Nano-enabled memory devices and anisotropic charge carrying arrays |
| US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
| US7816726B2 (en) | 2007-12-20 | 2010-10-19 | Promos Technologies Pte. Ltd. | Nonvolatile memories with laterally recessed charge-trapping dielectric |
| KR101010437B1 (ko) | 2008-07-15 | 2011-01-21 | 주식회사 동부하이텍 | 플래시 메모리 소자 및 그 제조 방법 |
| US20100163952A1 (en) * | 2008-12-31 | 2010-07-01 | Chia-Hong Jan | Flash Cell with Integrated High-K Dielectric and Metal-Based Control Gate |
| US8470670B2 (en) * | 2009-09-23 | 2013-06-25 | Infineon Technologies Ag | Method for making semiconductor device |
| US8101492B2 (en) * | 2009-09-23 | 2012-01-24 | Infineon Technologies Ag | Method for making semiconductor device |
| US8822329B2 (en) * | 2009-09-28 | 2014-09-02 | Infineon Technologies Ag | Method for making conductive interconnects |
| US8101477B1 (en) | 2010-09-28 | 2012-01-24 | Infineon Technologies Ag | Method for making semiconductor device |
| US9318336B2 (en) * | 2011-10-27 | 2016-04-19 | Globalfoundries U.S. 2 Llc | Non-volatile memory structure employing high-k gate dielectric and metal gate |
| US8951864B2 (en) * | 2012-02-13 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Split-gate device and method of fabricating the same |
| US9368644B2 (en) | 2013-12-20 | 2016-06-14 | Cypress Semiconductor Corporation | Gate formation memory by planarization |
| US9721958B2 (en) * | 2015-01-23 | 2017-08-01 | Silicon Storage Technology, Inc. | Method of forming self-aligned split-gate memory cell array with metal gates and logic devices |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278439A (en) * | 1991-08-29 | 1994-01-11 | Ma Yueh Y | Self-aligned dual-bit split gate (DSG) flash EEPROM cell |
| KR0172273B1 (ko) * | 1995-06-24 | 1999-02-01 | 김주용 | 플래쉬 메모리 셀의 제조방법 |
| US6261903B1 (en) * | 1998-05-14 | 2001-07-17 | Mosel Vitelic, Inc. | Floating gate method and device |
| TW449919B (en) * | 1998-12-18 | 2001-08-11 | Koninkl Philips Electronics Nv | A method of manufacturing a semiconductor device |
| US6432773B1 (en) * | 1999-04-08 | 2002-08-13 | Microchip Technology Incorporated | Memory cell having an ONO film with an ONO sidewall and method of fabricating same |
| EP1183732A1 (de) * | 2000-03-08 | 2002-03-06 | Koninklijke Philips Electronics N.V. | Halbleiterbauelement und dessen herstellungsverfahren |
| US6562681B2 (en) * | 2001-06-13 | 2003-05-13 | Mosel Vitelic, Inc. | Nonvolatile memories with floating gate spacers, and methods of fabrication |
-
2004
- 2004-02-13 US US10/546,748 patent/US7429513B2/en not_active Expired - Lifetime
- 2004-02-13 WO PCT/IB2004/050113 patent/WO2004077498A2/en not_active Ceased
- 2004-02-13 JP JP2006502590A patent/JP2006519491A/ja not_active Withdrawn
- 2004-02-13 AT AT04710959T patent/ATE518248T1/de not_active IP Right Cessation
- 2004-02-13 EP EP04710959A patent/EP1599908B1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| WO2004077498A2 (en) | 2004-09-10 |
| US7429513B2 (en) | 2008-09-30 |
| EP1599908B1 (de) | 2011-07-27 |
| JP2006519491A (ja) | 2006-08-24 |
| US20060166420A1 (en) | 2006-07-27 |
| WO2004077498A3 (en) | 2004-11-04 |
| EP1599908A2 (de) | 2005-11-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |