ATE519228T1 - Herstellungsverfahren für ein aktives gebiet und eine flache grabenisolation selbstjustiert zu einem tiefen graben - Google Patents

Herstellungsverfahren für ein aktives gebiet und eine flache grabenisolation selbstjustiert zu einem tiefen graben

Info

Publication number
ATE519228T1
ATE519228T1 AT00103964T AT00103964T ATE519228T1 AT E519228 T1 ATE519228 T1 AT E519228T1 AT 00103964 T AT00103964 T AT 00103964T AT 00103964 T AT00103964 T AT 00103964T AT E519228 T1 ATE519228 T1 AT E519228T1
Authority
AT
Austria
Prior art keywords
deep trench
deep
adjusted
production process
active area
Prior art date
Application number
AT00103964T
Other languages
English (en)
Inventor
Rama Divakaruni
Ulrike Gruening
Byeong Y Kim
Jack Mandelman
Larry Nesbit
Carl Radens
Original Assignee
Ibm
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Infineon Technologies Ag filed Critical Ibm
Application granted granted Critical
Publication of ATE519228T1 publication Critical patent/ATE519228T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
AT00103964T 1999-03-17 2000-02-25 Herstellungsverfahren für ein aktives gebiet und eine flache grabenisolation selbstjustiert zu einem tiefen graben ATE519228T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/271,124 US6184107B1 (en) 1999-03-17 1999-03-17 Capacitor trench-top dielectric for self-aligned device isolation

Publications (1)

Publication Number Publication Date
ATE519228T1 true ATE519228T1 (de) 2011-08-15

Family

ID=23034293

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00103964T ATE519228T1 (de) 1999-03-17 2000-02-25 Herstellungsverfahren für ein aktives gebiet und eine flache grabenisolation selbstjustiert zu einem tiefen graben

Country Status (6)

Country Link
US (1) US6184107B1 (de)
EP (1) EP1037281B1 (de)
JP (1) JP3496754B2 (de)
KR (1) KR100382294B1 (de)
AT (1) ATE519228T1 (de)
TW (1) TW466680B (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6602434B1 (en) * 1998-03-27 2003-08-05 Applied Materials, Inc. Process for etching oxide using hexafluorobutadiene or related fluorocarbons and manifesting a wide process window
US6153902A (en) * 1999-08-16 2000-11-28 International Business Machines Corporation Vertical DRAM cell with wordline self-aligned to storage trench
DE19944011B4 (de) * 1999-09-14 2007-10-18 Infineon Technologies Ag Verfahren zur Bildung mindestens zweier Speicherzellen eines Halbleiterspeichers
KR100436291B1 (ko) * 1999-11-09 2004-06-16 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 제조방법
US6432318B1 (en) * 2000-02-17 2002-08-13 Applied Materials, Inc. Dielectric etch process reducing striations and maintaining critical dimensions
US6573137B1 (en) * 2000-06-23 2003-06-03 International Business Machines Corporation Single sided buried strap
TW452879B (en) * 2000-07-27 2001-09-01 Promos Technologies Inc Method for removing polishing stop layer
US6509226B1 (en) * 2000-09-27 2003-01-21 International Business Machines Corporation Process for protecting array top oxide
JP4008352B2 (ja) * 2000-12-21 2007-11-14 東京エレクトロン株式会社 絶縁膜のエッチング方法
US7015145B2 (en) * 2001-01-08 2006-03-21 Infineon Technologies Ag Self-aligned collar and strap formation for semiconductor devices
US6541810B2 (en) * 2001-06-29 2003-04-01 International Business Machines Corporation Modified vertical MOSFET and methods of formation thereof
DE10152549A1 (de) * 2001-10-24 2003-05-15 Infineon Technologies Ag Verfahren zum Herstellen eines elektrischen Kontaktierungsbereichs in einer mikroelektronischen Halbleiterstruktur
DE10212610C1 (de) * 2002-03-21 2003-11-06 Infineon Technologies Ag Verfahren zur Erzeugung einer horizontalen Isolationsschicht auf einem leitenden Material in einem Graben
US6849518B2 (en) * 2002-05-07 2005-02-01 Intel Corporation Dual trench isolation using single critical lithographic patterning
US6620677B1 (en) * 2002-05-31 2003-09-16 Infineon Technologies Ag Support liner for isolation trench height control in vertical DRAM processing
US6635525B1 (en) 2002-06-03 2003-10-21 International Business Machines Corporation Method of making backside buried strap for SOI DRAM trench capacitor
TW589716B (en) * 2003-06-10 2004-06-01 Nanya Technology Corp Method of fabricating memory device having a deep trench capacitor
US6864151B2 (en) * 2003-07-09 2005-03-08 Infineon Technologies Ag Method of forming shallow trench isolation using deep trench isolation
US7034352B2 (en) * 2004-02-11 2006-04-25 Infineon Technologies Ag DRAM with very shallow trench isolation
US7679130B2 (en) * 2005-05-10 2010-03-16 Infineon Technologies Ag Deep trench isolation structures and methods of formation thereof
US7947569B2 (en) * 2008-06-30 2011-05-24 Infineon Technologies Austria Ag Method for producing a semiconductor including a foreign material layer
US7943449B2 (en) * 2008-09-30 2011-05-17 Infineon Technologies Austria Ag Semiconductor component structure with vertical dielectric layers
US20130187159A1 (en) 2012-01-23 2013-07-25 Infineon Technologies Ag Integrated circuit and method of forming an integrated circuit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5360758A (en) * 1993-12-03 1994-11-01 International Business Machines Corporation Self-aligned buried strap for trench type DRAM cells
US5895255A (en) 1994-11-30 1999-04-20 Kabushiki Kaisha Toshiba Shallow trench isolation formation with deep trench cap
US5643823A (en) * 1995-09-21 1997-07-01 Siemens Aktiengesellschaft Application of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structures
US5614431A (en) 1995-12-20 1997-03-25 International Business Machines Corporation Method of making buried strap trench cell yielding an extended transistor
US5909044A (en) * 1997-07-18 1999-06-01 International Business Machines Corporation Process for forming a high density semiconductor device
US5831301A (en) * 1998-01-28 1998-11-03 International Business Machines Corp. Trench storage dram cell including a step transfer device
US5945707A (en) * 1998-04-07 1999-08-31 International Business Machines Corporation DRAM cell with grooved transfer device
US6074909A (en) * 1998-07-31 2000-06-13 Siemens Aktiengesellschaft Apparatus and method for forming controlled deep trench top isolation layers

Also Published As

Publication number Publication date
US6184107B1 (en) 2001-02-06
JP2000277708A (ja) 2000-10-06
KR100382294B1 (ko) 2003-05-01
EP1037281B1 (de) 2011-08-03
EP1037281A1 (de) 2000-09-20
JP3496754B2 (ja) 2004-02-16
TW466680B (en) 2001-12-01
KR20000076882A (ko) 2000-12-26

Similar Documents

Publication Publication Date Title
ATE519228T1 (de) Herstellungsverfahren für ein aktives gebiet und eine flache grabenisolation selbstjustiert zu einem tiefen graben
KR960016773B1 (en) Buried bit line and cylindrical gate cell and forming method thereof
US5306659A (en) Reach-through isolation etching method for silicon-on-insulator devices
EP1033759A3 (de) MOS-Anordnung mit einer vergrabenen Gate und Verfahren zur Herstellung
EP1199745A3 (de) Vertikaltransitor-Grabenkondensator-DRAM mit SOI-Logikbauteilen
ATE533183T1 (de) Verfahren zur herstellung vertiefter zugangsvorrichtungen
KR20000058096A (ko) 동적 랜덤 액세스 메모리
SG73543A1 (en) A method for making improved shallow trench isolation for semiconductor integrated circuits
WO2003030244A8 (en) Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
EP1291907A3 (de) Verfahren zur Herstellung von Hochspannungshalbleiteranordnungen
TW359035B (en) FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures
JPS5681974A (en) Manufacture of mos type semiconductor device
EP0747941A3 (de) Verfahren zur Bildung von erhöhten Source- und Drainzonen in integrierten Schaltungen
WO2002084745A3 (en) Power semiconductor devices and methods of forming same
ATE363731T1 (de) Auf geringe leckage ausgerichtete architektur für sub 0,18 mikrometer salizidiertes cmos bauelement
TW356601B (en) Method for making memory cell of self-aligning field plate and structure of the same
ATE401665T1 (de) Verfahren zur selbstausrichtung einer damascenen gatterstruktur zu isolationsgebieten
WO2002073667A3 (en) Formation of a frontside contact on silicon-on-insulator substrate
EP0905771A3 (de) DRAM Zelle mit Grabenkondensator und Verfahren zu deren Herstellung
EP0905772A3 (de) DRAM Zelle mit Grabenkondensator und Verfahren zu deren Herstellung
GB0011692D0 (en) Method of forming a shallow trench isolation structure in a semiconductor device
DE50013674D1 (de) CMOS kompatibler SOI-Prozess
EP0872895A3 (de) Vertikaler Feldeffekttransistor mit isolierter Steuerelektrode, Verfahren zu dessen Herstellung und entsprechende integrierte Schaltung
KR970053454A (ko) 딥 트렌치와 샐로우 트렌치 조합형 소자분리 구조 및 그 제조방법
WO2002101824A3 (de) Dram-speicherzelle mit grabenkondensator und verfahren zu ihrer herstellung

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties