ATE520037T1 - Verfahren zur überwachung und anpassung einer schaltungsleistung - Google Patents

Verfahren zur überwachung und anpassung einer schaltungsleistung

Info

Publication number
ATE520037T1
ATE520037T1 AT08834058T AT08834058T ATE520037T1 AT E520037 T1 ATE520037 T1 AT E520037T1 AT 08834058 T AT08834058 T AT 08834058T AT 08834058 T AT08834058 T AT 08834058T AT E520037 T1 ATE520037 T1 AT E520037T1
Authority
AT
Austria
Prior art keywords
testing
monitoring
adjusting
bist
failures
Prior art date
Application number
AT08834058T
Other languages
English (en)
Inventor
Anand Dixit
Raymond Heald
Steven Boyle
Original Assignee
Oracle America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oracle America Inc filed Critical Oracle America Inc
Application granted granted Critical
Publication of ATE520037T1 publication Critical patent/ATE520037T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3187—Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT08834058T 2007-09-26 2008-09-24 Verfahren zur überwachung und anpassung einer schaltungsleistung ATE520037T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/861,403 US7797596B2 (en) 2007-09-26 2007-09-26 Method for monitoring and adjusting circuit performance
PCT/US2008/077511 WO2009042678A1 (en) 2007-09-26 2008-09-24 Method for monitoring and adjusting circuit performance

Publications (1)

Publication Number Publication Date
ATE520037T1 true ATE520037T1 (de) 2011-08-15

Family

ID=40042904

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08834058T ATE520037T1 (de) 2007-09-26 2008-09-24 Verfahren zur überwachung und anpassung einer schaltungsleistung

Country Status (5)

Country Link
US (1) US7797596B2 (de)
EP (1) EP2201396B1 (de)
CN (1) CN101981460B (de)
AT (1) ATE520037T1 (de)
WO (1) WO2009042678A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8140902B2 (en) * 2008-11-12 2012-03-20 International Business Machines Corporation Internally controlling and enhancing advanced test and characterization in a multiple core microprocessor
WO2010104428A1 (en) * 2009-03-10 2010-09-16 Saab Ab Built-in test system with prognostic capability and method
US8122312B2 (en) * 2009-04-14 2012-02-21 International Business Machines Corporation Internally controlling and enhancing logic built-in self test in a multiple core microprocessor
CN101984492B (zh) * 2010-06-11 2016-03-23 上海华虹宏力半导体制造有限公司 一种降低闪存待机功耗的结构及其方法
US9003244B2 (en) 2013-07-31 2015-04-07 International Business Machines Corporation Dynamic built-in self-test system
US9500705B2 (en) * 2013-08-28 2016-11-22 Wisconsin Alumni Research Foundation Integrated circuit providing fault prediction
US10141071B2 (en) * 2015-12-26 2018-11-27 Intel Corporation Predictive count fail byte (CFBYTE) for non-volatile memory
EP3432014A1 (de) * 2017-07-19 2019-01-23 Siemens Aktiengesellschaft Verfahren und system zur prädiktiven wartung von integrierten schaltungen
US10901023B2 (en) * 2018-08-09 2021-01-26 Nxp B.V. Apparatuses and methods involving adjustable circuit-stress test conditions for stressing regional circuits
DE112019005149T5 (de) 2018-10-15 2021-07-01 Nvidia Corporation Verbesserte in-system-testabdeckung basierend auf detektieren von komponentendegradation

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6795788B2 (en) * 2000-06-06 2004-09-21 Hewlett-Packard Development Company, L.P. Method and apparatus for discovery of operational boundaries for shmoo tests
JP3405713B2 (ja) * 2000-06-27 2003-05-12 松下電器産業株式会社 半導体装置の寿命推定方法および信頼性シミュレーション方法
US7309998B2 (en) * 2002-12-02 2007-12-18 Burns Lawrence M Process monitor for monitoring an integrated circuit chip
US7065676B1 (en) * 2002-12-27 2006-06-20 Unisys Corporation Multi-threaded memory management test system with feedback to adjust input parameters in response to performance
AU2003217641A1 (en) * 2003-02-20 2004-09-17 International Business Machines Corporation Integrated circuit testing methods using well bias modification
DE10334801B3 (de) * 2003-07-30 2005-01-27 Infineon Technologies Ag Halbleiterschaltung und Verfahren zum Testen, Überwachen und applikationsnahen Einstellen einer Halbleiterschaltung
US6900656B1 (en) * 2003-11-10 2005-05-31 Texas Instruments Incorporated Method of testing an integrated circuit and an integrated circuit test apparatus
JP4846223B2 (ja) 2004-10-12 2011-12-28 株式会社アドバンテスト 試験装置および試験方法
US7450452B2 (en) * 2006-06-23 2008-11-11 Texas Instruments Incorporated Method to identify or screen VMIN drift on memory cells during burn-in or operation
US20080040089A1 (en) * 2006-07-18 2008-02-14 Wendemagagnehu Beyene Efficient Characterization of High-Speed Circuits
US20080036487A1 (en) * 2006-08-09 2008-02-14 Arm Limited Integrated circuit wearout detection
US7385864B2 (en) * 2006-09-12 2008-06-10 Texas Instruments Incorporated SRAM static noise margin test structure suitable for on chip parametric measurements
US8103463B2 (en) * 2006-09-21 2012-01-24 Impact Technologies, Llc Systems and methods for predicting failure of electronic systems and assessing level of degradation and remaining useful life

Also Published As

Publication number Publication date
US20090083598A1 (en) 2009-03-26
US7797596B2 (en) 2010-09-14
WO2009042678A1 (en) 2009-04-02
CN101981460A (zh) 2011-02-23
EP2201396A1 (de) 2010-06-30
EP2201396B1 (de) 2011-08-10
CN101981460B (zh) 2014-06-04

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