ATE520991T1 - Integrierte schaltung, verfahren und elektronisches gerät - Google Patents

Integrierte schaltung, verfahren und elektronisches gerät

Info

Publication number
ATE520991T1
ATE520991T1 AT08172216T AT08172216T ATE520991T1 AT E520991 T1 ATE520991 T1 AT E520991T1 AT 08172216 T AT08172216 T AT 08172216T AT 08172216 T AT08172216 T AT 08172216T AT E520991 T1 ATE520991 T1 AT E520991T1
Authority
AT
Austria
Prior art keywords
operation state
integrated circuit
security
objects
security operation
Prior art date
Application number
AT08172216T
Other languages
English (en)
Inventor
Peter Svensson
Mikael Lostedt
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Application granted granted Critical
Publication of ATE520991T1 publication Critical patent/ATE520991T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Tests Of Electronic Circuits (AREA)
AT08172216T 2008-07-14 2008-12-18 Integrierte schaltung, verfahren und elektronisches gerät ATE520991T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US8041408P 2008-07-14 2008-07-14

Publications (1)

Publication Number Publication Date
ATE520991T1 true ATE520991T1 (de) 2011-09-15

Family

ID=41059634

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08172216T ATE520991T1 (de) 2008-07-14 2008-12-18 Integrierte schaltung, verfahren und elektronisches gerät

Country Status (5)

Country Link
US (1) US20110314541A1 (de)
EP (1) EP2146213B1 (de)
JP (1) JP5490114B2 (de)
AT (1) ATE520991T1 (de)
WO (1) WO2010006879A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201227391A (en) * 2010-12-16 2012-07-01 Walton Advanced Eng Inc Storage device with a hidden space and its operation method
US20130262192A1 (en) * 2012-03-29 2013-10-03 ATC Logistics & Electronics System and method for receiving quality issue log
US20150331043A1 (en) * 2014-05-15 2015-11-19 Manoj R. Sastry System-on-chip secure debug
US10687025B2 (en) * 2015-10-27 2020-06-16 Vivint, Inc. Anti-theft doorbell camera
US20190007212A1 (en) 2017-06-30 2019-01-03 Intel Corporation Secure unlock systems for locked devices
US20200341058A1 (en) * 2019-04-28 2020-10-29 Nuvoton Technology Corporation Time-limited debug mode

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698750A (en) * 1984-12-27 1987-10-06 Motorola, Inc. Security for integrated circuit microcomputer with EEPROM
US5293610A (en) * 1989-08-04 1994-03-08 Motorola, Inc. Memory system having two-level security system for enhanced protection against unauthorized access
JP3461234B2 (ja) * 1996-01-22 2003-10-27 株式会社東芝 データ保護回路
JP3421526B2 (ja) * 1997-02-14 2003-06-30 モトローラ株式会社 デ−タ処理装置
US6466048B1 (en) * 2001-05-23 2002-10-15 Mosaid Technologies, Inc. Method and apparatus for switchably selecting an integrated circuit operating mode
US7228440B1 (en) * 2002-02-13 2007-06-05 Lsi Corporation Scan and boundary scan disable mechanism on secure device
US7185249B2 (en) * 2002-04-30 2007-02-27 Freescale Semiconductor, Inc. Method and apparatus for secure scan testing
EP1560033A1 (de) * 2004-01-29 2005-08-03 STMicroelectronics S.A. Integrierte Schaltung mit sicherem Testmodus mittels Initialisierung des Testmodus
JP2005316734A (ja) * 2004-04-28 2005-11-10 Sony Corp 集積回路のモード設定方法及び装置
US8255700B2 (en) 2004-06-29 2012-08-28 Qualcomm Incorporated Lockstep mechanism to ensure security in hardware at power-up
JP2006053808A (ja) * 2004-08-13 2006-02-23 Fuji Electric Holdings Co Ltd 作業者認証管理システム
US7457960B2 (en) * 2004-11-30 2008-11-25 Analog Devices, Inc. Programmable processor supporting secure mode

Also Published As

Publication number Publication date
EP2146213A1 (de) 2010-01-20
EP2146213B1 (de) 2011-08-17
JP2011528144A (ja) 2011-11-10
WO2010006879A1 (en) 2010-01-21
US20110314541A1 (en) 2011-12-22
JP5490114B2 (ja) 2014-05-14

Similar Documents

Publication Publication Date Title
EP2256661A4 (de) Elektronisches endgerät, steuerverfahren und computerprogramm dafür sowie integrierter schaltkreis
ATE557331T1 (de) Elektronische vorrichtung und verfahren zur bereitstellung der verbesserten anzeige, dass eine alarmuhr eingeschaltet ist
WO2008008140A3 (en) Methods and apparatus for passive attachment of components for integrated circuits
DE602008006561D1 (de) Verfahren und vorrichtung zur erkennung von taktgattergelegenheiten bei einer elektronischen schaltung im pipeline-design
WO2007126487A3 (en) Power ok distribution for multi-voltage chips
ZA200702791B (en) Electronic device with three movable layers
WO2012146830A3 (en) Method and apparatus for increasing the functionality of an electronic device in a locked state
WO2008117583A1 (ja) 車両制御装置
WO2008035176A3 (en) System and method for look ahead detection of electrical problems at a motor of a vehicle
DE602004028765D1 (de) Tragbare elektronische einrichtungen mit multimodus-anpassschaltungen und betriebsverfahren dafür
HK1221515A1 (zh) 眼科装置上具有薄膜纳米晶体集成电路的眼科装置
ATE529786T1 (de) Elektronische vorrichtung und verfahren zur bereitstellung einer verbesserten verwaltung mehrerer zeiten aus mehreren zeitzonen
SG10201912788PA (en) System for testing an integrated circuit of a device and its method of use
DE602007011546D1 (de) Verdrahtungsmuster, elektronische Vorrichtung, organisches Halbleiterbauelement, geschichtetes Verdrahtungsmuster und geschichtetes Verdrahtungssubstrat mit dem Verdrahtungsmuster
WO2010004427A3 (en) Measurement device and measurement method
TW200745582A (en) Testing apparatus and testing module
GB2465104A (en) Electronic device interface control system
DE112009002568A5 (de) Integrierter Schaltungsbaustein, der einen Induktor enthält, und Verfahren
ATE551884T1 (de) Elektronisches gerät und verfahren zum untersuchen einer leiterplatte
WO2010120645A3 (en) Method and apparatus for secure configuration of electronic devices
EP2618254A3 (de) Zufallszahlengenerator
TWI349414B (en) Control circuit for power supply device, power supply device, and control method thereof
IL213536A0 (en) Device for testing an integrated circuit and method for implementing same
ATE550710T1 (de) System und verfahren zum disambiguieren von stricheingaben
JP2009042183A5 (de)

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties