ATE521032T1 - Computerbefehl mit befehlsabruf-steuerbit - Google Patents

Computerbefehl mit befehlsabruf-steuerbit

Info

Publication number
ATE521032T1
ATE521032T1 AT02737621T AT02737621T ATE521032T1 AT E521032 T1 ATE521032 T1 AT E521032T1 AT 02737621 T AT02737621 T AT 02737621T AT 02737621 T AT02737621 T AT 02737621T AT E521032 T1 ATE521032 T1 AT E521032T1
Authority
AT
Austria
Prior art keywords
command
memory
processing unit
control bit
computer
Prior art date
Application number
AT02737621T
Other languages
English (en)
Inventor
Jeroen Leijten
Original Assignee
Silicon Hive Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Hive Bv filed Critical Silicon Hive Bv
Application granted granted Critical
Publication of ATE521032T1 publication Critical patent/ATE521032T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Image Processing (AREA)
AT02737621T 2001-01-30 2002-01-04 Computerbefehl mit befehlsabruf-steuerbit ATE521032T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01200333 2001-01-30
PCT/IB2002/000025 WO2002061574A1 (en) 2001-01-30 2002-01-04 Computer instruction with instruction fetch control bits

Publications (1)

Publication Number Publication Date
ATE521032T1 true ATE521032T1 (de) 2011-09-15

Family

ID=8179827

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02737621T ATE521032T1 (de) 2001-01-30 2002-01-04 Computerbefehl mit befehlsabruf-steuerbit

Country Status (6)

Country Link
US (1) US7873813B2 (de)
EP (1) EP1358551B1 (de)
JP (1) JP3842218B2 (de)
KR (1) KR20030007480A (de)
AT (1) ATE521032T1 (de)
WO (1) WO2002061574A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1387256B1 (de) * 2002-07-31 2018-11-21 Texas Instruments Incorporated Programmzähleranpassung basiert auf der Erkennung eines Befehlspräfixes
JP2006500673A (ja) * 2002-09-24 2006-01-05 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 処理装置、処理方法及びコンパイラ
WO2005116819A1 (en) * 2004-05-27 2005-12-08 Koninklijke Philips Electronics N.V. Microprocessor and method of instruction alignment
AT501213B1 (de) * 2004-12-03 2006-10-15 On Demand Microelectronics Gmb Verfahren zum steuern der zyklischen zuführung von instruktionswörtern zu rechenelementen und datenverarbeitungseinrichtung mit einer solchen steuerung
JP2007226615A (ja) * 2006-02-24 2007-09-06 Matsushita Electric Ind Co Ltd 情報処理装置、圧縮プログラム生成方法及び情報処理システム
US9201655B2 (en) * 2008-03-19 2015-12-01 International Business Machines Corporation Method, computer program product, and hardware product for eliminating or reducing operand line crossing penalty
US9201652B2 (en) 2011-05-03 2015-12-01 Qualcomm Incorporated Methods and apparatus for storage and translation of entropy encoded software embedded within a memory hierarchy
US10120692B2 (en) * 2011-07-28 2018-11-06 Qualcomm Incorporated Methods and apparatus for storage and translation of an entropy encoded instruction sequence to executable form
CN104321774B (zh) * 2012-05-25 2018-08-28 皇家飞利浦有限公司 用于防逆向工程和/或篡改程序的方法、系统以及设备
US20140244932A1 (en) * 2013-02-27 2014-08-28 Advanced Micro Devices, Inc. Method and apparatus for caching and indexing victim pre-decode information

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437149A (en) 1980-11-17 1984-03-13 International Business Machines Corporation Cache memory architecture with decoding
DE69129872T2 (de) 1990-03-27 1999-03-04 Philips Electronics N.V., Eindhoven Datenverarbeitungssystem mit einem leistungsverbessernden Befehlscachespeicher
US5640526A (en) * 1994-12-21 1997-06-17 International Business Machines Corporation Superscaler instruction pipeline having boundary indentification logic for variable length instructions
WO1997043710A2 (en) 1996-05-15 1997-11-20 Philips Electronics N.V. Vliw processor which processes compressed instruction format
EP0912924A1 (de) 1996-07-16 1999-05-06 Advanced Micro Devices, Inc. Superskalar mikroprozessor mit schneller befehlsausrichtungseinheit
WO1998006042A1 (en) * 1996-08-07 1998-02-12 Sun Microsystems, Inc. Wide instruction unpack method and apparatus
US5870576A (en) 1996-12-16 1999-02-09 Hewlett-Packard Company Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition within an instruction cache containing pointers to compressed instructions for wide instruction word processor architectures
US5819058A (en) * 1997-02-28 1998-10-06 Vm Labs, Inc. Instruction compression and decompression system and method for a processor
US6134633A (en) * 1997-10-31 2000-10-17 U.S. Philips Corporation Prefetch management in cache memory
US6314509B1 (en) 1998-12-03 2001-11-06 Sun Microsystems, Inc. Efficient method for fetching instructions having a non-power of two size
US6546478B1 (en) * 1999-10-14 2003-04-08 Advanced Micro Devices, Inc. Line predictor entry with location pointers and control information for corresponding instructions in a cache line
US6684319B1 (en) * 2000-06-30 2004-01-27 Conexant Systems, Inc. System for efficient operation of a very long instruction word digital signal processor

Also Published As

Publication number Publication date
US20020116598A1 (en) 2002-08-22
WO2002061574A1 (en) 2002-08-08
US7873813B2 (en) 2011-01-18
KR20030007480A (ko) 2003-01-23
JP3842218B2 (ja) 2006-11-08
EP1358551A1 (de) 2003-11-05
JP2004519028A (ja) 2004-06-24
EP1358551B1 (de) 2011-08-17

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Legal Events

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