ATE521089T1 - N-kanal-mosfet mit doppelstressoren und verfahren zu ihrer herstellung - Google Patents

N-kanal-mosfet mit doppelstressoren und verfahren zu ihrer herstellung

Info

Publication number
ATE521089T1
ATE521089T1 AT07797521T AT07797521T ATE521089T1 AT E521089 T1 ATE521089 T1 AT E521089T1 AT 07797521 T AT07797521 T AT 07797521T AT 07797521 T AT07797521 T AT 07797521T AT E521089 T1 ATE521089 T1 AT E521089T1
Authority
AT
Austria
Prior art keywords
fet
carbon concentration
patterned stressor
stressors
double
Prior art date
Application number
AT07797521T
Other languages
English (en)
Inventor
Jinghong Li
Yaocheng Liu
Zhijiong Luo
Anita Madan
Nivo Rovedo
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE521089T1 publication Critical patent/ATE521089T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Amplifiers (AREA)
  • Measuring Fluid Pressure (AREA)
AT07797521T 2006-05-24 2007-05-17 N-kanal-mosfet mit doppelstressoren und verfahren zu ihrer herstellung ATE521089T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/420,047 US7279758B1 (en) 2006-05-24 2006-05-24 N-channel MOSFETs comprising dual stressors, and methods for forming the same
PCT/US2007/069100 WO2007140130A2 (en) 2006-05-24 2007-05-17 N-channel mosfets comprising dual stressors, and methods for forming the same

Publications (1)

Publication Number Publication Date
ATE521089T1 true ATE521089T1 (de) 2011-09-15

Family

ID=38562118

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07797521T ATE521089T1 (de) 2006-05-24 2007-05-17 N-kanal-mosfet mit doppelstressoren und verfahren zu ihrer herstellung

Country Status (6)

Country Link
US (2) US7279758B1 (de)
EP (1) EP2036130B1 (de)
CN (1) CN101523608B (de)
AT (1) ATE521089T1 (de)
TW (1) TWI459557B (de)
WO (1) WO2007140130A2 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006009272B4 (de) * 2006-02-28 2013-01-03 Globalfoundries Inc. Verfahren zur Herstellung eines verspannten Transistors durch eine späte Amorphisierung und durch zu entfernende Abstandshalter
DE102006019935B4 (de) * 2006-04-28 2011-01-13 Advanced Micro Devices, Inc., Sunnyvale SOI-Transistor mit reduziertem Körperpotential und ein Verfahren zur Herstellung
DE102006019921B4 (de) * 2006-04-28 2010-10-28 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung des Transistors mit eingebetteter Schicht mit Zugverformung mit geringem Abstand zu der Gateelektrode
US7279758B1 (en) * 2006-05-24 2007-10-09 International Business Machines Corporation N-channel MOSFETs comprising dual stressors, and methods for forming the same
US7625801B2 (en) * 2006-09-19 2009-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation with a pre-amorphous implant
US7892935B2 (en) * 2006-11-30 2011-02-22 United Microelectronics Corp. Semiconductor process
US20090035911A1 (en) * 2007-07-30 2009-02-05 Willy Rachmady Method for forming a semiconductor device having abrupt ultra shallow epi-tip regions
CN101447510B (zh) * 2007-11-27 2010-12-22 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US8048750B2 (en) * 2008-03-10 2011-11-01 Texas Instruments Incorporated Method to enhance channel stress in CMOS processes
US7524740B1 (en) 2008-04-24 2009-04-28 International Business Machines Corporation Localized strain relaxation for strained Si directly on insulator
JP5235486B2 (ja) * 2008-05-07 2013-07-10 パナソニック株式会社 半導体装置
US8623728B2 (en) * 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
US8836036B2 (en) * 2010-01-05 2014-09-16 Globalfoundries Singapore Pte. Ltd. Method for fabricating semiconductor devices using stress engineering
CN102130054B (zh) * 2010-01-20 2013-05-01 中芯国际集成电路制造(上海)有限公司 改善半导体器件的截止漏电流发散的方法
US8551845B2 (en) 2010-09-21 2013-10-08 International Business Machines Corporation Structure and method for increasing strain in a device
US20120153350A1 (en) * 2010-12-17 2012-06-21 Globalfoundries Inc. Semiconductor devices and methods for fabricating the same
CN102693916B (zh) * 2011-03-25 2015-01-14 中国科学院微电子研究所 改进MOSFETs镍基硅化物热稳定性的方法
CN102693917B (zh) * 2011-03-25 2015-07-08 中国科学院微电子研究所 热稳定性镍基硅化物源漏mosfets及其制造方法
US8592308B2 (en) 2011-07-20 2013-11-26 International Business Machines Corporation Silicided device with shallow impurity regions at interface between silicide and stressed liner
JP5802492B2 (ja) * 2011-09-09 2015-10-28 株式会社東芝 半導体素子及びその製造方法
US8916428B2 (en) * 2012-01-05 2014-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a semiconductor device
US20130193492A1 (en) * 2012-01-30 2013-08-01 International Business Machines Corporation Silicon carbon film structure and method
US9018690B2 (en) 2012-09-28 2015-04-28 Silicon Storage Technology, Inc. Split-gate memory cell with substrate stressor region, and method of making same
US8927375B2 (en) 2012-10-08 2015-01-06 International Business Machines Corporation Forming silicon-carbon embedded source/drain junctions with high substitutional carbon level
CN103811349A (zh) * 2012-11-06 2014-05-21 中国科学院微电子研究所 半导体结构及其制造方法
CN104217955B (zh) * 2013-06-05 2017-11-03 中芯国际集成电路制造(上海)有限公司 N型晶体管及其制作方法、互补金属氧化物半导体
US9419138B2 (en) 2014-09-29 2016-08-16 International Business Machines Corporation Embedded carbon-doped germanium as stressor for germanium nFET devices
US11011620B2 (en) 2016-09-27 2021-05-18 Intel Corporation Techniques for increasing channel region tensile strain in n-MOS devices
CN108962987B (zh) * 2017-05-19 2020-11-13 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
JP6852703B2 (ja) * 2018-03-16 2021-03-31 信越半導体株式会社 炭素濃度評価方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3443343B2 (ja) * 1997-12-03 2003-09-02 松下電器産業株式会社 半導体装置
US6368947B1 (en) 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
DE10034942B4 (de) 2000-07-12 2004-08-05 Infineon Technologies Ag Verfahren zur Erzeugung eines Halbleitersubstrats mit vergrabener Dotierung
KR100342306B1 (ko) * 2000-09-05 2002-07-02 윤종용 트랜지스터 및 이의 형성 방법
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6703293B2 (en) 2002-07-11 2004-03-09 Sharp Laboratories Of America, Inc. Implantation at elevated temperatures for amorphization re-crystallization of Si1-xGex films on silicon substrates
US6911379B2 (en) * 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US7112495B2 (en) * 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
CN100446272C (zh) * 2003-09-04 2008-12-24 台湾积体电路制造股份有限公司 应变沟道半导体结构
US6906360B2 (en) 2003-09-10 2005-06-14 International Business Machines Corporation Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
EP1524699B1 (de) 2003-10-17 2012-12-26 Imec Verfahren zur Herstellung CMOS Bauelementen mit einer kerbenförmigen Gatterisolierschicht und so erhaltene Vorrichtungen
US7303949B2 (en) 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
TWI222673B (en) * 2003-10-24 2004-10-21 Taiwan Semiconductor Mfg Substrate structure having relaxed thin-film layer with low defect-density and its manufacturing method
US7005333B2 (en) * 2003-12-30 2006-02-28 Infineon Technologies Ag Transistor with silicon and carbon layer in the channel region
US20050186722A1 (en) * 2004-02-25 2005-08-25 Kuan-Lun Cheng Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions
US7015108B2 (en) 2004-02-26 2006-03-21 Intel Corporation Implanting carbon to form P-type drain extensions
US7002209B2 (en) * 2004-05-21 2006-02-21 International Business Machines Corporation MOSFET structure with high mechanical stress in the channel
US7227205B2 (en) * 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
DE102004037087A1 (de) * 2004-07-30 2006-03-23 Advanced Micro Devices, Inc., Sunnyvale Selbstvorspannende Transistorstruktur und SRAM-Zellen mit weniger als sechs Transistoren
US7288448B2 (en) * 2004-08-24 2007-10-30 Orlowski Marius K Method and apparatus for mobility enhancement in a semiconductor device
US7067868B2 (en) * 2004-09-29 2006-06-27 Freescale Semiconductor, Inc. Double gate device having a heterojunction source/drain and strained channel
US7164163B2 (en) * 2005-02-22 2007-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with hybrid-strain inducing layer
JP4361886B2 (ja) * 2005-02-24 2009-11-11 富士通マイクロエレクトロニクス株式会社 半導体集積回路装置およびその製造方法
US7355221B2 (en) * 2005-05-12 2008-04-08 International Business Machines Corporation Field effect transistor having an asymmetrically stressed channel region
US7279758B1 (en) * 2006-05-24 2007-10-09 International Business Machines Corporation N-channel MOSFETs comprising dual stressors, and methods for forming the same

Also Published As

Publication number Publication date
US7473608B2 (en) 2009-01-06
WO2007140130A3 (en) 2009-04-09
TWI459557B (zh) 2014-11-01
TW200810119A (en) 2008-02-16
CN101523608A (zh) 2009-09-02
US7279758B1 (en) 2007-10-09
WO2007140130A2 (en) 2007-12-06
CN101523608B (zh) 2010-11-10
EP2036130B1 (de) 2011-08-17
US20070281413A1 (en) 2007-12-06
EP2036130A4 (de) 2009-12-23
EP2036130A2 (de) 2009-03-18

Similar Documents

Publication Publication Date Title
ATE521089T1 (de) N-kanal-mosfet mit doppelstressoren und verfahren zu ihrer herstellung
TW200741976A (en) Methods for fabricating a stressed MOS device
SG143174A1 (en) Method to form selective strained si using lateral epitaxy
JP2007324589A5 (de)
TW200729465A (en) An embedded strain layer in thin SOI transistors and a method of forming the same
GB2491778A (en) A P-Fet with a strained nanowire channel and embedded sige source and drain stressors
TW200802803A (en) Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions
WO2010056433A3 (en) OPTIMIZED COMPRESSIVE SiGe CHANNEL PMOS TRANSISTOR WITH ENGINEERED Ge PROFILE AND OPTIMIZED SILICON CAP LAYER
SG155957A1 (en) Method to control source/drain stressor profiles for stress engineering
WO2006066194A3 (en) Strained nmos transistor featuring deep carbon doped regions and raised donor doped source and drain
DE602007008611D1 (de) Spannungsverstärkter mos-transistor und verfahren zu seiner herstellung
TW200605322A (en) Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility
ATE504078T1 (de) Verfahren zur herstellung von cmos-transistoren mit verspanntem halbleiter mit gitterfehlangepassten regionen
ATE527693T1 (de) Feldeffekttransistor mit einer oxydschicht als kanalschicht und verfahren zu dessen herstellung
WO2007130333A3 (en) Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors
WO2009120612A3 (en) Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
WO2005043591A3 (en) HIGH PERFORMANCE STRESS-ENHANCED MOSFETs USING Si:C AND SiGe EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE
TW200625466A (en) MOSFET device with localized stressor
SG133478A1 (en) Modulation of stress in stress film through ion implantation and its application in stress memorization technique
WO2006023219A3 (en) Method and apparatus for mobility enhancement in a semiconductor device
SG153817A1 (en) Formation of raised source/drain structures in nfet with embedded sige in pfet
TW200711148A (en) Stressed field effect transistors on hybrid orientation substrate
TW200746313A (en) A tensile strained NMOS transistor using group III-N source/drain regions
TW200638543A (en) Hybrid-strained sidewall spacer for CMOS process
GB2457411A (en) Stress enhanced transistor and methods for its fabrication

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties