ATE523990T1 - Integrierte schaltung mit datenkommunikationsnetz und verfahren zum entwurf integrierter schaltungen - Google Patents

Integrierte schaltung mit datenkommunikationsnetz und verfahren zum entwurf integrierter schaltungen

Info

Publication number
ATE523990T1
ATE523990T1 AT06727978T AT06727978T ATE523990T1 AT E523990 T1 ATE523990 T1 AT E523990T1 AT 06727978 T AT06727978 T AT 06727978T AT 06727978 T AT06727978 T AT 06727978T AT E523990 T1 ATE523990 T1 AT E523990T1
Authority
AT
Austria
Prior art keywords
data
network
integrated circuit
communications network
data communications
Prior art date
Application number
AT06727978T
Other languages
English (en)
Inventor
John Dielissen
Edwin Rijpkema
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=36694308&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE523990(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE523990T1 publication Critical patent/ATE523990T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/22—Traffic shaping
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/56—Routing software
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9021—Plurality of buffers per packet

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
AT06727978T 2005-04-21 2006-04-20 Integrierte schaltung mit datenkommunikationsnetz und verfahren zum entwurf integrierter schaltungen ATE523990T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05103232 2005-04-21
PCT/IB2006/051218 WO2006111931A1 (en) 2005-04-21 2006-04-20 Integrated circuit with data communication network and ic design method

Publications (1)

Publication Number Publication Date
ATE523990T1 true ATE523990T1 (de) 2011-09-15

Family

ID=36694308

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06727978T ATE523990T1 (de) 2005-04-21 2006-04-20 Integrierte schaltung mit datenkommunikationsnetz und verfahren zum entwurf integrierter schaltungen

Country Status (7)

Country Link
US (1) US8072893B2 (de)
EP (1) EP1875683B1 (de)
JP (1) JP2008538670A (de)
KR (1) KR20080011209A (de)
CN (1) CN101164298A (de)
AT (1) ATE523990T1 (de)
WO (1) WO2006111931A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100653087B1 (ko) * 2005-10-17 2006-12-01 삼성전자주식회사 ＡＸＩ가 적용된 ＮｏＣ 시스템 및 그 인터리빙 방법
JP5753372B2 (ja) * 2009-12-22 2015-07-22 キヤノン株式会社 データ処理装置およびその制御方法
US8604833B2 (en) 2010-01-26 2013-12-10 Freescale Semiconductor, Inc. Integrated circuit device and method of using combinatorial logic in a data processing circuit
US9355690B1 (en) * 2011-03-17 2016-05-31 Xilinx, Inc. Time-multiplexed, asynchronous device
EP2700202B1 (de) * 2011-04-20 2017-11-08 NXP USA, Inc. Integrierte schaltung und verfahren zur durchführung von cut-through-weiterleitung
IN2014DE02931A (de) 2013-11-01 2015-06-26 Seiko Epson Corp
CN104615388B (zh) * 2013-11-01 2017-12-22 精工爱普生株式会社 打印控制系统
US10110700B2 (en) * 2014-03-31 2018-10-23 Oracle International Corporation Multiple on-die communication networks
US10176012B2 (en) 2014-12-12 2019-01-08 Nxp Usa, Inc. Method and apparatus for implementing deterministic response frame transmission
US10505757B2 (en) 2014-12-12 2019-12-10 Nxp Usa, Inc. Network interface module and a method of changing network configuration parameters within a network device
US9787571B2 (en) 2014-12-22 2017-10-10 Intel Corporation Link delay based routing apparatus for a network-on-chip
US9965410B2 (en) * 2016-01-21 2018-05-08 Qualcomm Incorporated Priority-based data communication over multiple communication buses
US10628352B2 (en) 2016-07-19 2020-04-21 Nxp Usa, Inc. Heterogeneous multi-processor device and method of enabling coherent data access within a heterogeneous multi-processor device
EP3776241B1 (de) * 2018-03-31 2023-06-28 Micron Technology, Inc. Loop-thread-befehlsausführungssteuerung für eine selbstplanende rekonfigurierbare multithread-rechenmatrix

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6466548B1 (en) * 1998-10-28 2002-10-15 Cisco Technology, Inc. Hop by hop quality of service measurement system
US7606164B2 (en) * 1999-12-14 2009-10-20 Texas Instruments Incorporated Process of increasing source rate on acceptable side of threshold
US20020087716A1 (en) * 2000-07-25 2002-07-04 Shakeel Mustafa System and method for transmitting customized multi priority services on a single or multiple links over data link layer frames
US7197009B1 (en) * 2002-03-06 2007-03-27 Sprint Communications Company L.P. Delay variation based routing in communication systems
GB2399263A (en) * 2003-03-07 2004-09-08 Zarlink Semiconductor Ltd Clock synchronisation over a packet network
US7680920B2 (en) * 2003-03-24 2010-03-16 Netiq Corporation Methods, systems and computer program products for evaluating network performance using diagnostic rules identifying performance data to be collected
US7362763B2 (en) * 2003-09-04 2008-04-22 Samsung Electronics Co., Ltd. Apparatus and method for classifying traffic in a distributed architecture router

Also Published As

Publication number Publication date
EP1875683A1 (de) 2008-01-09
KR20080011209A (ko) 2008-01-31
EP1875683B1 (de) 2011-09-07
WO2006111931A1 (en) 2006-10-26
US8072893B2 (en) 2011-12-06
CN101164298A (zh) 2008-04-16
JP2008538670A (ja) 2008-10-30
US20080186983A1 (en) 2008-08-07

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