ATE525699T1 - Verbindungsnetz mit dynamischen unternetzen - Google Patents

Verbindungsnetz mit dynamischen unternetzen

Info

Publication number
ATE525699T1
ATE525699T1 AT10164557T AT10164557T ATE525699T1 AT E525699 T1 ATE525699 T1 AT E525699T1 AT 10164557 T AT10164557 T AT 10164557T AT 10164557 T AT10164557 T AT 10164557T AT E525699 T1 ATE525699 T1 AT E525699T1
Authority
AT
Austria
Prior art keywords
information transfer
subnetworks
dynamic
transfer bus
connecting network
Prior art date
Application number
AT10164557T
Other languages
English (en)
Inventor
Francois Jacquet
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE525699T1 publication Critical patent/ATE525699T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AT10164557T 2009-06-08 2010-06-01 Verbindungsnetz mit dynamischen unternetzen ATE525699T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0953780A FR2946441A1 (fr) 2009-06-08 2009-06-08 Reseau d'interconnexions a sous-reseaux dynamiques.

Publications (1)

Publication Number Publication Date
ATE525699T1 true ATE525699T1 (de) 2011-10-15

Family

ID=41479200

Family Applications (1)

Application Number Title Priority Date Filing Date
AT10164557T ATE525699T1 (de) 2009-06-08 2010-06-01 Verbindungsnetz mit dynamischen unternetzen

Country Status (5)

Country Link
US (1) US8397009B2 (de)
EP (1) EP2264610B1 (de)
JP (1) JP5595796B2 (de)
AT (1) ATE525699T1 (de)
FR (1) FR2946441A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2951868B1 (fr) * 2009-10-28 2012-04-06 Kalray Briques de construction d'un reseau sur puce
JP6313237B2 (ja) 2015-02-04 2018-04-18 東芝メモリ株式会社 ストレージシステム

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2036350A5 (de) * 1969-03-12 1970-12-24 Commissariat Energie Atomique
DE3714385A1 (de) * 1987-04-30 1988-11-10 Philips Patentverwaltung Verfahren und schaltungsanordnung zur koppelfeldsteuerung in einem vermittlungssystem
US5218240A (en) * 1990-11-02 1993-06-08 Concurrent Logic, Inc. Programmable logic cell and array with bus repeaters
JPH06314264A (ja) * 1993-05-06 1994-11-08 Nec Corp セルフ・ルーティング・クロスバー・スイッチ
US5602844A (en) * 1994-11-15 1997-02-11 Xerox Corporation Self routing crossbar switch suitable for use as a switching fabric in an ATM switch
US5930256A (en) * 1997-03-28 1999-07-27 Xerox Corporation Self-arbitrating crossbar switch
US6480927B1 (en) * 1997-12-31 2002-11-12 Unisys Corporation High-performance modular memory system with crossbar connections
US6970967B2 (en) * 2002-06-18 2005-11-29 Texas Instruments Incorporated Crossbar circuit having a plurality of repeaters forming different repeater arrangements
JP2006260127A (ja) * 2005-03-17 2006-09-28 Hiroshima Univ 結合網およびそれを用いたマルチポートメモリ
KR100655081B1 (ko) * 2005-12-22 2006-12-08 삼성전자주식회사 가변적 액세스 경로를 가지는 멀티 포트 반도체 메모리장치 및 그에 따른 방법
US7769942B2 (en) * 2006-07-27 2010-08-03 Rambus, Inc. Cross-threaded memory system
US7925816B2 (en) * 2006-11-06 2011-04-12 Oracle America, Inc. Architecture for an output buffered switch with input groups
CA2705234A1 (en) * 2007-11-09 2009-05-14 Plurality Ltd. Shared memory system for a tightly-coupled multiprocessor
JP5599969B2 (ja) * 2008-03-19 2014-10-01 ピーエスフォー ルクスコ エスエイアールエル マルチポートメモリ、および該マルチポートメモリを備えるコンピュータシステム
US7791976B2 (en) * 2008-04-24 2010-09-07 Qualcomm Incorporated Systems and methods for dynamic power savings in electronic memory operation
US8417863B2 (en) * 2010-07-16 2013-04-09 Apple Inc. Synchronous bus driving with repeaters

Also Published As

Publication number Publication date
EP2264610A1 (de) 2010-12-22
US8397009B2 (en) 2013-03-12
FR2946441A1 (fr) 2010-12-10
JP5595796B2 (ja) 2014-09-24
US20100312939A1 (en) 2010-12-09
EP2264610B1 (de) 2011-09-21
JP2010282627A (ja) 2010-12-16

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Legal Events

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