ATE526629T1 - Verfahren und vorrichtung zum prüfen eines systems auf einem chip unter beteiligung von parallelen und seriellen zugriffen - Google Patents

Verfahren und vorrichtung zum prüfen eines systems auf einem chip unter beteiligung von parallelen und seriellen zugriffen

Info

Publication number
ATE526629T1
ATE526629T1 AT08858340T AT08858340T ATE526629T1 AT E526629 T1 ATE526629 T1 AT E526629T1 AT 08858340 T AT08858340 T AT 08858340T AT 08858340 T AT08858340 T AT 08858340T AT E526629 T1 ATE526629 T1 AT E526629T1
Authority
AT
Austria
Prior art keywords
chip
testing
present
serial access
algorithmic
Prior art date
Application number
AT08858340T
Other languages
English (en)
Inventor
Tapan Chakraborty
Chen-Huan Chiang
Suresh Goyal
Michele Portolan
Treuren Bradford Van
Original Assignee
Alcatel Lucent
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Lucent filed Critical Alcatel Lucent
Application granted granted Critical
Publication of ATE526629T1 publication Critical patent/ATE526629T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT08858340T 2007-12-04 2008-11-25 Verfahren und vorrichtung zum prüfen eines systems auf einem chip unter beteiligung von parallelen und seriellen zugriffen ATE526629T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/950,138 US7958479B2 (en) 2007-12-04 2007-12-04 Method and apparatus for describing and testing a system-on-chip
PCT/US2008/013110 WO2009073120A1 (en) 2007-12-04 2008-11-25 Method and apparatus for testing a system-on-chip involving parallel and serial accesses

Publications (1)

Publication Number Publication Date
ATE526629T1 true ATE526629T1 (de) 2011-10-15

Family

ID=40419118

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08858340T ATE526629T1 (de) 2007-12-04 2008-11-25 Verfahren und vorrichtung zum prüfen eines systems auf einem chip unter beteiligung von parallelen und seriellen zugriffen

Country Status (8)

Country Link
US (1) US7958479B2 (de)
EP (1) EP2232373B1 (de)
JP (1) JP5188580B2 (de)
KR (1) KR101204138B1 (de)
CN (1) CN101884031B (de)
AT (1) ATE526629T1 (de)
ES (1) ES2374483T3 (de)
WO (1) WO2009073120A1 (de)

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US7949915B2 (en) * 2007-12-04 2011-05-24 Alcatel-Lucent Usa Inc. Method and apparatus for describing parallel access to a system-on-chip
US7962885B2 (en) * 2007-12-04 2011-06-14 Alcatel-Lucent Usa Inc. Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing
US7886263B1 (en) * 2007-12-10 2011-02-08 Cadence Design Systems, Inc. Testing to prescribe state capture by, and state retrieval from scan registers
US7954022B2 (en) * 2008-01-30 2011-05-31 Alcatel-Lucent Usa Inc. Apparatus and method for controlling dynamic modification of a scan path
US7958417B2 (en) * 2008-01-30 2011-06-07 Alcatel-Lucent Usa Inc. Apparatus and method for isolating portions of a scan path of a system-on-chip
CN103675576B (zh) * 2012-09-18 2016-02-10 英业达科技有限公司 基于边界扫描的芯片连接测试系统及其方法
US9310433B2 (en) * 2014-04-18 2016-04-12 Breker Verification Systems Testing SOC with portable scenario models and at different levels
US9727679B2 (en) * 2014-12-20 2017-08-08 Intel Corporation System on chip configuration metadata
US11403452B2 (en) * 2015-10-20 2022-08-02 Synopsys, Inc. Logic yield learning vehicle with phased design windows
CN106932705A (zh) * 2015-12-30 2017-07-07 深圳市中兴微电子技术有限公司 一种系统级封装多芯片互联测试方法及装置
US11156664B2 (en) * 2018-10-31 2021-10-26 SK Hynix Inc. Scan chain techniques and method of using scan chain structure
US10866283B2 (en) 2018-11-29 2020-12-15 Nxp B.V. Test system with embedded tester
US10983159B2 (en) * 2018-12-20 2021-04-20 International Business Machines Corporation Method and apparatus for wiring multiple technology evaluation circuits
US11327872B2 (en) * 2019-05-07 2022-05-10 Viavi Solutions Inc. Test instrument for software communications architecture device testing
CN112039728B (zh) * 2020-08-27 2021-05-18 中国科学院地质与地球物理研究所 端口通信测试方法及端口通信测试盒
CN114742008A (zh) * 2022-04-06 2022-07-12 桂林电子科技大学 一种icl实例化网络的布图规划设计方法
US20230018793A1 (en) * 2022-09-22 2023-01-19 Intel Corporation Programmable Input And Output Interfaces In Processing Integrated Circuits For Servers And Other Devices
CN117741411A (zh) * 2024-02-19 2024-03-22 西安简矽技术有限公司 一种芯片的调校系统和方法

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US4872169A (en) * 1987-03-06 1989-10-03 Texas Instruments Incorporated Hierarchical scan selection
GB9622687D0 (en) * 1996-10-31 1997-01-08 Sgs Thomson Microelectronics An integrated circuit with tap controller
US6708144B1 (en) * 1997-01-27 2004-03-16 Unisys Corporation Spreadsheet driven I/O buffer synthesis process
US6606588B1 (en) * 1997-03-14 2003-08-12 Interuniversitair Micro-Elecktronica Centrum (Imec Vzw) Design apparatus and a method for generating an implementable description of a digital system
US6456961B1 (en) * 1999-04-30 2002-09-24 Srinivas Patil Method and apparatus for creating testable circuit designs having embedded cores
US6430718B1 (en) * 1999-08-30 2002-08-06 Cypress Semiconductor Corp. Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom
US6587981B1 (en) * 1999-11-29 2003-07-01 Agilent Technologies, Inc. Integrated circuit with scan test structure
US7181705B2 (en) * 2000-01-18 2007-02-20 Cadence Design Systems, Inc. Hierarchical test circuit structure for chips with multiple circuit blocks
US6631504B2 (en) * 2000-01-18 2003-10-07 Cadence Design Systems, Inc Hierarchical test circuit structure for chips with multiple circuit blocks
US6665828B1 (en) * 2000-09-19 2003-12-16 International Business Machines Corporation Globally distributed scan blocks
JP3955196B2 (ja) * 2001-09-05 2007-08-08 富士通株式会社 試験回路および半導体集積回路装置
KR100430074B1 (ko) * 2002-01-08 2004-05-03 학교법인 한양학원 시스템칩 테스트 접근을 위한 랩드 코아 연결 모듈
US6678875B2 (en) * 2002-01-25 2004-01-13 Logicvision, Inc. Self-contained embedded test design environment and environment setup utility
US20040002832A1 (en) * 2002-05-20 2004-01-01 Chan Patrick P. Method and apparatus for boundary scan of serial interfaces
ATE347112T1 (de) * 2003-02-10 2006-12-15 Koninkl Philips Electronics Nv Testen von integrierten schaltungen
US20050097416A1 (en) 2003-10-31 2005-05-05 Dominic Plunkett Testing of integrated circuits using boundary scan
KR100514319B1 (ko) * 2003-12-02 2005-09-13 조상욱 시스템 온 칩의 테스트를 위한 코아 접속 스위치
US7356745B2 (en) * 2004-02-06 2008-04-08 Texas Instruments Incorporated IC with parallel scan paths and compare circuitry
WO2005078465A1 (en) 2004-02-17 2005-08-25 Institut National Polytechnique De Grenoble Integrated circuit chip with communication means enabling remote control of testing means of ip cores of the integrated circuit
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US7188330B2 (en) * 2004-05-18 2007-03-06 Lsi Logic Corporation Handling of unused coreware with embedded boundary scan chains to avoid the need of a boundary scan synthesis tool during custom instance creation
JP4388903B2 (ja) * 2005-02-09 2009-12-24 富士通マイクロエレクトロニクス株式会社 Ｊｔａｇ試験方式
US7502979B2 (en) * 2005-06-10 2009-03-10 Altera Corporation Pipelined scan structures for testing embedded cores
US7610568B2 (en) * 2005-10-20 2009-10-27 Agere Systems Inc. Methods and apparatus for making placement sensitive logic modifications
ATE462980T1 (de) * 2005-10-24 2010-04-15 Nxp Bv Ic-testverfahren und vorrichtung
US7962885B2 (en) * 2007-12-04 2011-06-14 Alcatel-Lucent Usa Inc. Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing
US7949915B2 (en) * 2007-12-04 2011-05-24 Alcatel-Lucent Usa Inc. Method and apparatus for describing parallel access to a system-on-chip
US7954022B2 (en) * 2008-01-30 2011-05-31 Alcatel-Lucent Usa Inc. Apparatus and method for controlling dynamic modification of a scan path
US7958417B2 (en) * 2008-01-30 2011-06-07 Alcatel-Lucent Usa Inc. Apparatus and method for isolating portions of a scan path of a system-on-chip

Also Published As

Publication number Publication date
US7958479B2 (en) 2011-06-07
CN101884031B (zh) 2013-07-24
CN101884031A (zh) 2010-11-10
US20090144594A1 (en) 2009-06-04
EP2232373B1 (de) 2011-09-28
ES2374483T3 (es) 2012-02-17
KR20100084186A (ko) 2010-07-23
KR101204138B1 (ko) 2012-11-22
JP2011505643A (ja) 2011-02-24
JP5188580B2 (ja) 2013-04-24
EP2232373A1 (de) 2010-09-29
WO2009073120A1 (en) 2009-06-11

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